An all static CMOS ADPLL fabricated in 65 nm digital CMOS SOI technology has a fully programmable proportional-integral-differential (PID) loop filter and features a third order delta sigma modulator. The DCO is a three stage, static inverter based ring oscillator programmable in 768 frequency steps. The ADPLL lock range is 500 MHz to 8 GHz at 1.3 V and 25degC, and 90 MHz to 1.2 GHz at 0.5 V and 100degC. The IC dissipates 8 mW/GHz at 1.2 V and 1.6 mW/GHz at 0.5 V. The synthesized 4 GHz clock has a period jitter of 0.7 ps rms, and long term jitter of 6 ps rms. The phase noise under nominal operating conditions is 112 dBc/Hz measured at a 10 MHz offset from a 4 GHz center frequency. The total circuit area is 200 mum 150 mum.

A Wide Power Supply Range, Wide Tuning Range, All Static CMOS All Digital PLL in 65 nm SOI

In this brief, a systematic design procedure for a second-order all-digital phase-locked loop (PLL) is proposed. The design procedure is based on the analogy between a type-II second-order analog PLL and an all-digital PLL. The all-digital PLL design inherits the frequency response and stability characteristics of the analog prototype PLL

/pdf/a-design-procedure-for-all-digital-phase-locked-loops-based-310m2nuszw.pdf

A Design Procedure for All-Digital Phase-Locked Loops Based on a Charge-Pump Phase-Locked-Loop Analogy

In this paper, a 2.5 b/stage pipelined time-to-digital converter (TDC) is presented. For pipelined operation, a novel time-register is proposed which is capable of storing, adding and subtracting time information with a clock signal. Together with a pulse-train time-amplifier, a 9-bit synchronous pipelined TDC is implemented, which consists of three 2.5 b/stage TDCs and a 3 b delay-line TDC. A prototype chip fabricated in 65 nm CMOS process achieves 1.12 ps of time resolution at 250 MS/s while consuming 15.4 mW. Compared to other high-resolution state-of-the-art TDCs, the proposed pipelined TDC achieves the best figure-of-merit (FoM) without any calibration.

A 9 bit, 1.12 ps Resolution 2.5 b/Stage Pipelined Time-to-Digital Converter in 65 nm CMOS Using Time-Register

The resolution of multi-bit linear TDC is closely related to process technology since the minimum resolvable time quantity is proportional to one-inverter delay [1]. For fine time resolution, vernier delay chains are frequently used [2,3]. Since the time resolution is determined by the difference between two inverter delays, a large number of inverter stages is required to cover a large detection range, resulting in long conversion time and high power consumption. Well-established data-conversion architectures have also been sought to achieve both large detection range and high resolution [4,5]. The two-step TDC was proposed to improve both the resolution and detectable range by amplifying the time residue after the coarse conversion for the fine conversion [4]. But, the previous time amplification schemes [4, 6] use metastability and suffer from small input range and gain uncertainties due to nonlinearity and PVT variations. This paper presents a power-efficient and wide dynamic range sub-exponent TDC. Based on a cascaded chain of 2× time amplifiers, the TDC generates the exponent-only information for the fractional time difference.

A 1 GHz ADPLL With a 1.25 ps Minimum-Resolution Sub-Exponent TDC in 0.18 $\mu$ m CMOS

In this paper, a novel pulse-train time amplifier is proposed that achieves linear, accurate, and programmable gain for a wide input range. Using the proposed pulse-train time amplifier, a 7-bit two-step TDC is implemented. The proposed TDC employs repetitive pulses with gated delay-lines for a calibration-free and programmable time amplification and quantization. The prototype chip fabricated in 65 nm CMOS process achieves 3.75 ps of time resolution at 200 MS/s while consuming 3.6 mW and occupying 0.02 mm2 area. Compared to previously reported TDCs, the proposed TDC achieves the fastest conversion rate and the best FoM without any calibration.

A 7 bit, 3.75 ps Resolution Two-Step Time-to-Digital Converter in 65 nm CMOS Using Pulse-Train Time Amplifier

A new dual-loop digital phase-locked loop (DPLL) architecture is presented. It employs a stochastic time-to-digital converter (STDC) and a high-frequency delta-sigma dithering to achieve wide PLL bandwidth and low jitter at the same time. The STDC exploits the stochastic properties of a set of latches to achieve high resolution. A prototype DPLL test chip has been fabricated in a 0.13-mum CMOS process, features a 0.7-1.7-GHz oscillator tuning range and a 6.9-ps rms jitter, and consumes 17 mW under 1.2-V supply while operating at 1.2 GHz.

/pdf/a-digital-pll-with-a-stochastic-time-to-digital-converter-1fuv8zsyj6.pdf

A Digital PLL With a Stochastic Time-to-Digital Converter

A new frequency detector, which allows for a fast frequency lock of phase-locked loops (PLLs), is presented. It uses the feedback divider that already exists in a PLL to determine the frequency difference. The proposed frequency detector provides frequency difference information at each reference cycle, and thus guarantees fast frequency acquisition.

Frequency detector for fast frequency lock of digital PLLs

A new dual-loop digital PLL (DPLL) architecture is presented. It employs a stochastic time-to-digital converter (STDC) and a high frequency delta-sigma dithering to achieve a wide PLL bandwidth and low jitter at the same time. The test chip has been fabricated in a 0.13mum CMOS process. The DPLL features a 0.7-1.7 GHz oscillator tuning range, 6.9ps rms jitter and consumes 17mW while operating at 1.2GHz

/pdf/a-digital-pll-with-a-stochastic-time-to-digital-converter-5azb7b3gsk.pdf

A Digital PLL with a Stochastic Time-to-Digital Converter

Supply and ground noise sensitivity of a wide variety of ring and LC oscillators has been analyzed based on the perturbation projection vector (PPV) technique. The resulting PPV provides an understanding of how specific frequency content of supply/ground noise is converted to oscillator phase noise. Based on this analysis oscillators that are tolerant of supply/ground noise can be identified and used for low noise oscillator design.

/pdf/analysis-of-supply-and-ground-noise-sensitivity-in-ring-and-2y2jocuyx9.pdf

V. Kratyuk

Papers

A Design Procedure for All-Digital Phase-Locked Loops Based on a Charge-Pump Phase-Locked-Loop Analogy

A Digital PLL With a Stochastic Time-to-Digital Converter

Frequency detector for fast frequency lock of digital PLLs

A Digital PLL with a Stochastic Time-to-Digital Converter

Analysis of supply and ground noise sensitivity in ring and LC oscillators