ESD Phenomena and Test Methods The Physics of ESD Protection Circuit Elements Requirements and Synthesis of ESD Protection Circuits Design and Layout Requirements Analysis and Case Studies Modelling of ESD in Integrated Circuits Effects of Processing and Packaging.

ESD in silicon integrated circuits

A web or film is electrostatically charged by sequentially subjecting the web or film to a series of electric fields such that adjacent electric fields have substantially opposite polarities. Both a method and apparatus are disclosed for charging the web or film.

Method and apparatus for the electrostatic charging of a web or film

The trends in ESD robustness as a function of technology scaling, for feature sizes down to 0.25 /spl mu/m, have been experimentally determined using single finger nMOS transistors and full ESD protection circuits. It is shown that as feature sizes are reduced, good ESD performance can be obtained provided the negative effects of the shallower junctions are offset by the positive effects of the reduction in the effective channel lengths. Hence, processes and protection circuits with feature sizes as small as 0.25 /spl mu/m can be developed without degrading ESD robustness. >

The impact of technology scaling on ESD robustness and protection circuit design

This paper discusses state-of-the-art electrostatic discharge (ESD) protection in advanced semiconductor technologies and emerging technologies. ESD physics, semiconductor process issues, device and circuit simulation, circuits, and devices are examined.

The state of the art of electrostatic discharge protection: physics, technology, circuits, design, simulation, and scaling

This paper provides a detailed description of the IBM SiGe BiCMOS and rf CMOS technologies. The technologies provide high-performance SiGe heterojunction bipolar transistors (HBTs) combined with advanced CMOS technology and a variety of passive devices critical for realizing an integrated mixed-signal system-on-a-chip (SoC). The paper reviews the process development and integration methodology, presents the device characteristics, and shows how the development and device selection were geared toward usage in mixed-signal IC development.

Foundation of rf CMOS and SiGe BiCMOS technologies

A novel snubber-clamped diode-string ESD protection circuit for mixed voltage interface microprocessor applications is described. Analytical models, circuit simulation, electrical characterization, ESD electrothermal simulation, ESD test data, and an ESD analytical failure model are shown for shallow trench isolation (STI) and LOCOS CMOS technologies.

Analysis of snubber-clamped diode-string mixed voltage interface ESD protection network for advanced microprocessors

Scaling, optimization and design considerations of electrostatic discharge protection circuits in CMOS technology

Suppression of particle generation in a modified clean room corona air ionizer

Electrostatic discharge (ESD) protection in silicon-on-insulator (SOI) semiconductor technology is perceived as a major roadblock for the SOI technology to become a viable mainstream contender for high-performance advanced CMOS semiconductor chips (Hu, 1994; Colinge, 1991). In this paper, our results in four successive SOI technology generations demonstrate that excellent ESD protection levels are achievable in SOI chips with no additional masking steps, process implants, costs or ESD design area. ESD results also show that the ESD robustness of the SOI ESD device is improving with partially depleted SOI MOSFET scaling from 0.25 to 0.12 /spl mu/m L/sub eff/ technology generations (Shahidi et al., 1999; Voldman et al., 1995, 1997, 1999). By allowing the ESD network minimum design to scale with the technology, improved ESD results are evident in each generation with no indication of any SOI-specific ESD limitations. For future technology generations below 1.5 V V/sub DD/ power supply, continued improvement is anticipated due to buried-oxide scaling, lower trigger voltages, dynamic threshold voltage MOSFET (DTMOS) techniques and ESD I/O design learning (Voldman et al, 1997; Assaderaghi et al., 1994). ESD protection of partially depleted SOI technology is not a problem or technology concern using our proposed ESD methodology.

Vaughn P. Gross

Papers

Analysis of snubber-clamped diode-string mixed voltage interface ESD protection network for advanced microprocessors

Scaling, optimization and design considerations of electrostatic discharge protection circuits in CMOS technology

Suppression of particle generation in a modified clean room corona air ionizer

Electrostatic discharge protection in silicon-on-insulator technology

CMOS-on-SOI ESD protection networks