Learn the basic properties and designs of modern VLSI devices, as well as the factors affecting performance, with this thoroughly updated second edition. The first edition has been widely adopted as a standard textbook in microelectronics in many major US universities and worldwide. The internationally-renowned authors highlight the intricate interdependencies and subtle tradeoffs between various practically important device parameters, and also provide an in-depth discussion of device scaling and scaling limits of CMOS and bipolar devices. Equations and parameters provided are checked continuously against the reality of silicon data, making the book equally useful in practical transistor design and in the classroom. Every chapter has been updated to include the latest developments, such as MOSFET scale length theory, high-field transport model, and SiGe-base bipolar devices.

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Fundamentals of Modern VLSI Devices

The pace of the development of silicon photonics has quickened since 2004 due to investment by industry and government. Commercial state-of-the-art CMOS silicon-on-insulator (SOI) foundries are now being utilized in a crucial test of 1.55-mum monolithic optoelectronic (OE) integration, a test sponsored by the Defense Advanced Research Projects Agency (DARPA). The preliminary results indicate that the silicon photonics are truly CMOS compatible. RD however, lasing has not yet been attained. The new paradigm for the Si-based photonic and optoelectric integrated circuits is that these chip-scale networks, when suitably designed, will operate at a wavelength anywhere within the broad spectral range of 1.2-100 mum, with cryocooling needed in some cases

The Past, Present, and Future of Silicon Photonics

The role of extended and point defects, and key impurities such as C, O, and H, on the electrical and optical properties of GaN is reviewed. Recent progress in the development of high reliability contacts, thermal processing, dry and wet etching techniques, implantation doping and isolation, and gate insulator technology is detailed. Finally, the performance of GaN-based electronic and photonic devices such as field effect transistors, UV detectors, laser diodes, and light-emitting diodes is covered, along with the influence of process-induced or grown-in defects and impurities on the device physics.

Gan : processing, defects, and devices

An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

This review article attempts to provide a comprehensive review of the recent progress in the so-called resistive random access memories (RRAMs) First, a brief introduction is presented to describe the construction and development of RRAMs, their potential for broad applications in the fields of nonvolatile memory, unconventional computing and logic devices, and the focus of research concerning RRAMs over the past decade Second, both inorganic and organic materials used in RRAMs are summarized, and their respective advantages and shortcomings are discussed Third, the important switching mechanisms are discussed in depth and are classified into ion migration, charge trapping/de-trapping, thermochemical reaction, exclusive mechanisms in inorganics, and exclusive mechanisms in organics Fourth, attention is given to the application of RRAMs for data storage, including their current performance, methods for performance enhancement, sneak-path issue and possible solutions, and demonstrations of 2-D and 3-D crossbar arrays Fifth, prospective applications of RRAMs in unconventional computing, as well as logic devices and multi-functionalization of RRAMs, are comprehensively summarized and thoroughly discussed The present review article ends with a short discussion concerning the challenges and future prospects of the RRAMs

Recent progress in resistive random access memories: Materials, switching mechanisms, and performance

Long and short buried-channel In0.7Ga0.3As MOSFETs with and without alpha-Si passivation are demonstrated. Devices with alpha-Si passivation show much higher transconductance and an effective peak mobility of 3810 cm2/ V middots. Short-channel MOSFETs with a gate length of 160 nm display a current of 825 muA/mum at Vg - Vt = 1.6 V and peak transconductance of 715 muS/mum. In addition, the virtual source velocity extracted from the short-channel devices is 1.4-1.7 times higher than that of Si MOSFETs. These results indicate that the high-performance In0.7Ga0.3 As-channel MOSFETs passivated by an alpha -Si layer are promising candidates for advanced post-Si CMOS applications.

High-Performance $\hbox{In}_{0.7}\hbox{Ga}_{0.3}\hbox{As}$ -Channel MOSFETs With High- $\kappa$ Gate Dielectrics and $\alpha$ -Si Passivation

In this letter, we demonstrate the effectiveness of the controlled spalling technology for producing high-efficiency (28.7%) thin-film InGaP/(In)GaAs/Ge tandem solar cells. The controlled spalling technique was employed to separate the as-grown solar cell structure from the host Ge wafer followed by its transfer to an arbitrary Si support substrate. The structural and electrical properties of the thin-film tandem cells were examined and compared against those on the original bulk Ge substrate. The comparison of the electrical data suggests the equivalency in cell parameters for both the thin-film (spalled) and bulk (non-spalled) cells, confirming that the controlled spalling technology does maintain the integrity of all layers in such an elaborate solar cell structure.

High-efficiency thin-film InGaP/InGaAs/Ge tandem solar cells enabled by controlled spalling technology

Highly effective passivation of GaAs surface is achieved by a thin amorphous Si (a-Si) cap, deposited by plasma enhanced chemical vapor deposition method. Capacitance voltage measurements show that carrier accumulation or inversion layer is readily formed in response to an applied electrical field when GaAs is passivated with a-Si. High performance inversion mode n-channel GaAs metal-oxide-semiconductor field-effect transistors (MOSFETs) were fabricated with an a-Si/high-k/metal gate stack. Drain current in saturation region of 220mA∕mm with a mobility of 885cm2∕Vs were obtained at a gate overdrive voltage of 3.25V in MOSFETs with 5μm gate length.

Inversion mode n-channel GaAs field effect transistor with high-k/metal gate

This article describes various techniques for applying strain to current and future complementary metal–oxide–semiconductor (CMOS) channels to boost CMOS performance. A brief history of both biaxial and uniaxial strain engineering in planar CMOS technology is discussed. Scalability challenges associated with process-induced uniaxial strain in sub-22 nm CMOS is highlighted in view of shrinking device dimensions and 3D device architecture (such as fin field-effect transistors [FinFETs]). Non-uniform strain relaxation in patterned geometries in tight pitch two- and three-dimensional devices is addressed. A case is made that the future scalable strain platform will require a combination of biaxial strain at wafer level in conjunction with local uniaxial strain. Finally, potential application of strain engineering to advanced III–V metal oxide semiconductor FET channels will be examined.

https://www.cambridge.org/core/services/aop-cambridge-core/content/view/S0883769414000050

Strain scaling for CMOS

We report the first demonstration of 200 mm InGaAs-on-insulator (InGaAs-o-I) fabricated by the direct wafer bonding technique with a donor wafer made of III-V heteroepitaxial structure grown on 200 mm silicon wafer. The measured threading dislocation density of the In0.53Ga0.47As (InGaAs) active layer is equal to 3.5 × 109 cm−2, and it does not degrade after the bonding and the layer transfer steps. The surface roughness of the InGaAs layer can be improved by chemical-mechanical-polishing step, reaching values as low as 0.4 nm root-mean-square. The electron Hall mobility in 450 nm thick InGaAs-o-I layer reaches values of up to 6000 cm2/Vs, and working pseudo-MOS transistors are demonstrated with an extracted electron mobility in the range of 2000–3000 cm2/Vs. Finally, the fabrication of an InGaAs-o-I substrate with the active layer as thin as 90 nm is achieved with a Buried Oxide of 50 nm. These results open the way to very large scale production of III-V-o-I advanced substrates for future CMOS technology nodes.

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D. K. Sadana

Papers

High-Performance $\hbox{In}_{0.7}\hbox{Ga}_{0.3}\hbox{As}$ -Channel MOSFETs With High- $\kappa$ Gate Dielectrics and $\alpha$ -Si Passivation

High-efficiency thin-film InGaP/InGaAs/Ge tandem solar cells enabled by controlled spalling technology

Inversion mode n-channel GaAs field effect transistor with high-k/metal gate

Strain scaling for CMOS

Towards large size substrates for III-V co-integration made by direct wafer bonding on Si