Staf Verhaegen

TL;DR: This paper focuses on the aspect of design splitting and lithography for double patterning the poly layer of 32nm logic cells using the Synopsys full-chip physical verification and OPC conversion platforms and establishes guidelines for doublepatterning conversions and presents a new design rule fordouble patterning compliance checking applicable to full- chip scale.

TL;DR: This work documented the resolution limitations of single exposure, and double-patterning with the latest hyper-NA immersion tools and with fully optimized source conditions and demonstrated the best known methods to improve design decomposition in an effort to minimize the impact of mask-to-mask registration and process variance.

TL;DR: In this article, the benefit of freeform over traditional illumination is evaluated by applying source mask co-optimization for an aggressive use case, and wafer-based verification, for a 22 nm node SRAM of 0.099 μm² and 0.078 μm 2 ======bit cell area.

TL;DR: The ability to meet key physical design goals such as: reduce circuit area; minimize rework; ensure DPT compliance; guarantee patterning robustness on individual layer targets; ensure symmetric wafer results; and create uniform wafer density for the individual patterning layers is evaluated.

TL;DR: Three leading model-based OPC software packages with 193 nm lithography on random logic poly gate designs for the 0.13 micrometer generation are evaluated and the results indicate that the maturity of the model-OPC software tools for 193nm lithography is generally good, although specific improvements are recommended.