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Philosophical Transactions of the Royal Society

Annual Review of Materials Science

Amorphous indium zinc oxide (IZO) thin films were deposited at different temperatures, by atomic layer deposition (ALD) using [1,1,1-trimethyl-N-(trimethylsilyl)silanaminato]indium (INCA-1) as the indium precursor, diethlzinc (DEZ) as the zinc precursor, and hydrogen peroxide (H2O2) as the reactant. The ALD process of IZO deposition was carried by repeated supercycles, including one cycle of indium oxide (In2O3) and one cycle of zinc oxide (ZnO). The IZO growth rate deviates from the sum of the respective In2O3 and ZnO growth rates at ALD growth temperatures of 150, 175, and 200 °C. We propose growth temperature-dependent surface reactions during the In2O3 cycle that correspond with the growth-rate results. Thin-film transistors (TFTs) were fabricated with the ALD-grown IZO thin films as the active layer. The amorphous IZO TFTs exhibited high mobility of 42.1 cm2 V–1 s–1 and good positive bias temperature stress stability. Finally, flexible IZO TFT was successfully fabricated on a polyimide substrate with...

Flexible and High-Performance Amorphous Indium Zinc Oxide Thin-Film Transistor Using Low-Temperature Atomic Layer Deposition

We demonstrate charge trapping memory devices comprising aluminum oxide phosphate (ALPO) blocking/indium gallium zinc oxide charge-trapping/ALPO tunneling layers with a bottom-gated architecture fabricated by sol-gel process technique at temperatures as low as 300 °C. The memory device offers a large memory hysteresis of 13.5 V in the Id–Vg curve when the gate voltage is swept from −20 to +30 V and back. The true program-erase (P/E) window of 7 V is established for the P/E square pulse of ±20 V s−1. Good retention characteristic is confirmed within the experimental limit of 104 s. The P/E mechanism is illustrated by the complete band structure of the memory devices. We also demonstrate a control device without a charge trapping layer, which shows excellent thin film transistor characteristics.

All inorganic solution processed three terminal charge trapping memory device

Pt nanodots have been grown on Al2O3 film via atomic layer deposition (ALD) using (MeCp)Pt(Me)3 and O2 precursors. Influence of the substrate temperature, pulse time of (MeCp)Pt(Me)3, and deposition cycles on ALD Pt has been studied comprehensively by scanning electron microscopy, transmission electron microscopy, and X-ray photoelectron spectroscopy. Therefore, Pt nanodots with a high density of approximately 2 × 1012 cm-2 have been achieved under optimized conditions: 300°C substrate temperature, 1 s pulse time of (MeCp)Pt(Me)3, and 70 deposition cycles. Further, metal-oxide-semiconductor capacitors with Pt nanodots embedded in ALD Al2O3 dielectric have been fabricated and characterized electrically, indicating noticeable electron trapping capacity, efficient programmable and erasable characteristics, and good charge retention.

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Atomic layer deposition of high-density Pt nanodots on Al2O3 film using (MeCp)Pt(Me)3 and O2 precursors for nonvolatile memory applications.

A novel Zn-doped Al2O3 (ZAO) layer prepared by atomic layer deposition (ALD) is used as the charge storage medium in an In-Ga-Zn-O thin-film-transistor memory. The gate insulating stack of Al2O3/ZAO/Al2O3 is assembled in a single ALD step, and is found to possess a high electron storage capacity due to very deep defect levels. The memory device shows a threshold voltage shift as large as 6.38 V after a +15V/1 ms programming pulse, and quite good charge retention. Once programmed, the memory can be only light erased. The underlying mechanisms are discussed with the assistance of density functional theory calculations.

Novel Zn-Doped ${\rm Al}_{2}{\rm O}_{3}$ Charge Storage Medium for Light-Erasable In–Ga–Zn–O TFT Memory

Semiconducting amorphous indium-gallium-zinc oxide (a-IGZO) films are integrated with an Al2O3/Pt-nanocrystals/ Al2O3 gate-stack to form UV-erasable thin-film transistor (TFT) memory. The threshold voltage (Vth), subthreshold swing, ION/IOFF ratio, and effective electron mobility of the fabricated devices are 2.1 V, 0.39 V/decade, ~106, and 8.4 cm2/V·s, respectively. A positive Vth shift of 2.25 V is achieved after 1-ms programming at 10 V, whereas a negative Vth shift as large as 3.48 V is attained after 5-s UV erasing. In addition, a 10-year memory window of 2.56 V is extrapolated at room temperature. This high-performance a-IGZO TFT memory is suitable for optical touch-panel applications.

Unique UV-Erasable In-Ga-Zn-O TFT Memory With Self-Assembled Pt Nanocrystals

We studied how electrical erasing of indium gallium zinc oxide-thin-film-transistor memory was improved by adding concurrent irradiation with monochromatic light (ML). At fixed gate bias, irradiating at wavelengths of ≤500 nm increased the erasing window (ΔVth-e) significantly: At a gate bias of −20 V and an erasing time of 5 min, ML irradiation at 400 nm increased ΔVth-e from 0.29 to 3.21 V. ΔVth-e increased incrementally with gate bias, erasing time, and ML power density, particularly at short ML wavelengths. Analyzing our experimental results, we discuss the underlying erasure mechanisms.

Monochromatic light-assisted erasing effects of In-Ga-Zn-O thin film transistor memory with Al2O3/Zn-doped Al2O3/Al2O3 stacks

Metal-insulator-metal (MIM) capacitors with full atomic-layer-deposition Al
 2
O
 3
/ZrO
 2
/SiO
 2
/ZrO
 2
/Al
 2
O
 3
 stacks were explored for the first time. As the incorporated SiO
 2
 film thickness increased from 0 to 3 nm, the quadratic and linear voltage coefficients of capacitance (α and β) of the MIM capacitors reduced significantly from positive values to negative ones. For the stack with 3-nm SiO
 2
 film, a capacitance density of 7.40 fF/μm
 2
, α of -121 ppm/V
 2
, and β of -116 ppm/V were achieved, together with very low leakage current densities of 3.08 × 10
 -8
 A/cm
 2
 at 5 V at room temperature (RT) and 5.89 × 10
 -8
 A/cm
 2
 at 3.3 V at 125 °C, high breakdown field of 6.05 MV/cm, and high operating voltage of 6.3 V for a 10-year lifetime at RT. Thus, this type of stacks is a very promising candidate for next generation radio frequency and analog/mixed-signal integrated circuits.

Full ALD Al 2 O 3 /ZrO 2 /SiO 2 /ZrO 2 /Al 2 O 3 Stacks for High-Performance MIM Capacitors

The disclosure, belonging to the technological field of semiconductor memory, specifically relates to a semi-floating-gate device which comprises at least a semiconductor substrate, a source region, a drain region, a floating gate, a control gate, a perpendicular channel region and a gated p-n junction diode used to connect the floating gate and the substrate. The semi-floating-gate device disclosed in the disclosure using the floating gate to store information and realizing charging or discharging of the floating gate through a gated p-n junction diode boasts small unit area, high chip density, low operating voltage in data storage and strong ability in data retain.

Wei Zhang

Papers

Novel Zn-Doped ${\rm Al}_{2}{\rm O}_{3}$ Charge Storage Medium for Light-Erasable In–Ga–Zn–O TFT Memory

Unique UV-Erasable In-Ga-Zn-O TFT Memory With Self-Assembled Pt Nanocrystals

Monochromatic light-assisted erasing effects of In-Ga-Zn-O thin film transistor memory with Al2O3/Zn-doped Al2O3/Al2O3 stacks

Full ALD Al 2 O 3 /ZrO 2 /SiO 2 /ZrO 2 /Al 2 O 3 Stacks for High-Performance MIM Capacitors

Semi-floating gate device and manufacturing method therefor