Recent advances in flexible and stretchable electronics (FSE), a technology diverging from the conventional rigid silicon technology, have stimulated fundamental scientific and technological research efforts. FSE aims at enabling disruptive applications such as flexible displays, wearable sensors, printed RFID tags on packaging, electronics on skin/organs, and Internet-of-things as well as possibly reducing the cost of electronic device fabrication. Thus, the key materials components of electronics, the semiconductor, the dielectric, and the conductor as well as the passive (substrate, planarization, passivation, and encapsulation layers) must exhibit electrical performance and mechanical properties compatible with FSE components and products. In this review, we summarize and analyze recent advances in materials concepts as well as in thin-film fabrication techniques for high-k (or high-capacitance) gate dielectrics when integrated with FSE-compatible semiconductors such as organics, metal oxides, quantum...

High- k Gate Dielectrics for Emerging Flexible and Stretchable Electronics

To improve color reproduction areas in a display device having light-emitting elements. A display region has a plurality of picture elements. Each picture element includes: first and second pixels each including a light-emitting element which has a chromaticity whose x-coordinate in a CIE-XY chromaticity diagram is 0.50 or more; third and fourth pixels each including a light-emitting element which has a chromaticity whose y-coordinate in the diagram is 0.55 or more; and fifth and sixth pixels each including a light-emitting element which has a chromaticity whose x-coordinate and y-coordinate in the diagram are 0.20 or less and 0.25 or less, respectively. The light-emitting elements in the first and second pixels have different emission spectrums from each other; the light-emitting elements in the third and fourth pixels have different emission spectrums from each other; and the light-emitting elements in the fifth and sixth pixels have different emission spectrums from each other.

Display device and electronic device

An ultrathin, 5 nm, Al2O3 film grown by atomic-layer deposition was used as a gate dielectric for amorphous indium-gallium-zinc oxide (a-IGZO) thin-film transistors (TFTs). The Al2O3 layer showed a low surface roughness of 0.15 nm, a low leakage current, and a high breakdown voltage of 6 V. In particular, a very high gate capacitance of 720 nF/cm2 was achieved, making it possible for the a-IGZO TFTs to not only operate at a low voltage of 1 V but also exhibit desirable properties including a low threshold voltage of 0.3 V, a small subthreshold swing of 100 mV/decade, and a high on/off current ratio of 1.2 × 107. Furthermore, even under an ultralow operation voltage of 0.6 V, well-behaved transistor characteristics were still observed with an on/off ratio as high as 3 × 106. The electron transport through the Al2O3 layer has also been analyzed, indicating the Fowler–Nordheim tunneling mechanism.

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Low voltage operation of IGZO thin film transistors enabled by ultrathin Al2O3 gate dielectric

High-performance a-IGZO TFT with ZrO2 gate dielectric fabricated at room temperature

Indium–gallium–zinc-oxide thin-film transistors (TFTs) with solution-processed, high-capacitance Al x O y gate dielectrics have been fabricated at room temperature. The morphology and electrical properties of the anodized, ultra-thin Al x O y film have been studied. Several anodization voltages were used to create the gate dielectrics and the results showed that the TFTs gated with aluminum oxide anodized at 2.3 V (~3 nm) exhibited the best performance. The TFTs operate at an ultra-low voltage of 1 V with a high current on/off ratio >105 and a subthreshold swing ( SS ) as low as 68 mV/dec, which is very close to the theoretical limit of SS at 300 K. As a result, the presented devices possess a great potential for low-power electronics.

One-Volt IGZO Thin-Film Transistors With Ultra-Thin, Solution-Processed Al x O y Gate Dielectric

Low-voltage amorphous indium–gallium–zinc oxide (a-IGZO) thin-film transistors (TFTs) with thin HfO2 gate dielectric grown by anodic oxidation (anodization) method are investigated. The morphological and electrical properties of the anodized thin HfO2 film are studied. It is shown that the as-grown HfO2 film with an equivalent oxide thickness of 3.8 nm has a low leakage current density of $3.6 \times 10^{-8}$ A/cm $^{2}$ at 1 MV/cm and high dielectric constant of $\sim 21.$ The room-temperature fabricated a-IGZO TFTs with the anodized HfO2 gate dielectrics exhibit a low threshold voltage of −0.15 ± 0.08 V, small subthreshold swing value of 109 ± 4 mV/decade, reasonable saturation mobility of 8.1 ± 0.2 cm $^{2}$ /Vs, and an ON/OFF current ratio exceeding $1 \times 10^{7}$ .

Low-Voltage a-InGaZnO Thin-Film Transistors With Anodized Thin HfO 2 Gate Dielectric

The effect of O2 flow rate during the sputtered deposition of channel layer on the negative gate-bias stress (NGBS)-induced threshold voltage (Vth) instability of a-IGZO TFTs is investigated. It is shown that the negative gate-bias stress results in a negative Vth shift of the a-IGZO TFTs, and the shift amount decreases with the increase in O2 flow rate. It is proposed that the Vth shift originates from the electron-detrapping from the oxygen vacancy-related donor-like states at the channel/dielectric interface. As the O2 flow rate increases, the density of donor-like states is decreased and the distribution of neutral donor-like states below EF is also reduced. Therefore, the amount of Vth shift caused by the positively charged trap states and electrons injecting into the channel from the donor-like states decreases with the O2 flow rate increase. It is also shown experimentally that while the electrical characteristics of the a-IGZO TFTs are generally improved with the O2 flow rate increase, they are degraded if an excess O2 is introduced. An optimal O2/Ar flow rate ratio of about 5 sccm/45 sccm is suggested to make a trade-off between the electrical performances and the gate-bias stress-induced Vth instability.

Effect of ${\rm O}_{2}$ Flow Rate During Channel Layer Deposition on Negative Gate Bias Stress-Induced $V_{\rm th}$ Shift of a-IGZO TFTs

Disclosed is a method for manufacturing a self-aligned metal oxide thin film transistor. According to the present invention, a metal oxide semiconductor layer having a high carrier concentration is formed, and then a channel region which is self-aligned with a gate electrode is oxidized by a plasma having oxidbillity so that the channel region has a low carrier concentration and the source and drain regions have high carrier concentrations while the resulting transistor has a self-aligned structure. In addition, the threshold voltage of the transistor is controlled by the conditions under which the channel region of the transistor is subsequently oxidized by plasma having oxidbillity at a low temperature. Therefore, the controllability of the characteristics of the transistor is improved significantly, and the manufacturing process is simplified.

Method for manufacturing self-aligned thin film transistor

A dual-gate (DG) amorphous indium–gallium–zinc-oxide thin-film transistor (TFT)-driven pixel circuit for active-matrix organic light-emitting diode displays is presented. One gate of the DGs serves as a primary gate (PG) and the other as an auxiliary gate (AG). The threshold voltage ( $V_{\mathrm {{TH}}}$ ) of the DG TFT under the PG operation is modulated by the AG bias voltage. The $V_{\mathrm {{TH}}}$ variation ( $\Delta V_{\mathrm {{TH}}}$ ) is compensated with the AG and the drain diode-connected structure. The validity of the presented pixel circuit is experimentally verified. The measured current error rates are less than 3.2% at a $\Delta V_{\mathrm {{TH}}}$ of $\text {TFT} = \pm 0.5$ V and a $\Delta V_{\mathrm {{TH}}}$ of OLED = 0.5 V with the emission current ranging from 7 nA to $1.13~\mu \text{A}$ .

One Gate Diode-Connected Dual-Gate a-IGZO TFT Driven Pixel Circuit for Active Matrix Organic Light-Emitting Diode Displays

A simple method of fabricating fully self-aligned double-gate (SADG) homojunction a-IGZO TFTs is proposed and experimentally demonstrated for the first time The self-alignment between the bottom- and top-gates is realized with one backside-illuminated photolithographic step; and that between the source/drain regions and the two gates is formed by both argon plasma treatment and hydrogen doping The resulting overlap between the gate and source/drain regions is about 03 μm Excellent symmetry between bidirectional transfer characteristics in the fabricated SADG TFTs is observed Moreover, the dynamic threshold voltage operation is well demonstrated, and the driving capability, electrical stress effects under tied and separate gate biases are investigated

Xin He

Papers

Low-Voltage a-InGaZnO Thin-Film Transistors With Anodized Thin HfO 2 Gate Dielectric

Effect of ${\rm O}_{2}$ Flow Rate During Channel Layer Deposition on Negative Gate Bias Stress-Induced $V_{\rm th}$ Shift of a-IGZO TFTs

Method for manufacturing self-aligned thin film transistor

One Gate Diode-Connected Dual-Gate a-IGZO TFT Driven Pixel Circuit for Active Matrix Organic Light-Emitting Diode Displays

Implementation of Fully Self-Aligned Homojunction Double-Gate a-IGZO TFTs