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Yajun Ha
Researcher at ShanghaiTech University
Publications - 144
Citations - 1712
Yajun Ha is an academic researcher from ShanghaiTech University. The author has contributed to research in topics: Computer science & Field-programmable gate array. The author has an hindex of 19, co-authored 125 publications receiving 1426 citations. Previous affiliations of Yajun Ha include Chinese Academy of Sciences & Agency for Science, Technology and Research.
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Interference-Minimized Multipath Routing with Congestion Control in Wireless Sensor Network for High-Rate Streaming
TL;DR: This work proposes an interference- minimized multipath routing (I2MR) protocol that increases throughput by discovering zone-disjoint paths for load balancing, requiring minimal localization support and proposes a congestion control scheme that further increased throughput by loading the paths forload balancing at the highest possible rate supportable.
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FPGA-Based 40.9-Gbits/s Masked AES With Area Optimization for Storage Area Network
TL;DR: This brief aims to optimize the area for a masked AES with an unrolled structure by reducing the number of mapping and inverse mapping operations of the masked SubBytes step from ten to one and using FPGA block RAM (BRAM) to further reduce hardware resources.
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An Ultra-Low-Energy Multi-Standard JPEG Co-Processor in 65 nm CMOS With Sub/Near Threshold Supply Voltage
TL;DR: A design technique for (near) subthreshold operation that achieves ultra low energy dissipation at throughputs of up to 100 MB/s suitable for digital consumer electronic applications and is largely applicable to designing other sound/graphic and streaming processors.
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Multiprocessor systems synthesis for multiple use-cases of multiple applications on FPGA
TL;DR: Techniques are presented to merge multiple use-cases into one hardware design to minimize cost and design time, making it well suited for fast design-space exploration (DSE) in MPSoC systems.
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A Low Active Leakage and High Reliability Phase Change Memory (PCM) Based Non-Volatile FPGA Storage Element
TL;DR: The proposed nvSRAM-based FPGA system significantly accelerates the loading speed to less than 1 ns with 2.54 fJ/cell loading energy and achieves 174 times reduction in active leakage power and 15,000 times increase in retention time.