Yi Song

TL;DR: Uniform, array-based InP nanostructures with lateral dimensions as small as sub-20 nm and AR > 35 are demonstrated using inverse metal-assisted chemical etching (I-MacEtch) in hydrogen peroxide and sulfuric acid, a purely solution-based yet anisotropic etching method.

TL;DR: In this paper, the III-V junctionless gate-all-around (GAA) nanowire MOSFETs are experimentally demonstrated for the first time.

TL;DR: The aggressive downscaling of complementary metal–oxide–semiconductor (CMOS) technology to the sub-21-nm technology node is facing great challenges, and innovative technologies such as metal gate/high-k dielectric integration, source/drain engineering, mobility enhancement technology, new device architectures, and enhanced quasiballistic transport channels serve as possible solutions for nanoscaled CMOS.

TL;DR: A field effect transistor structure comprises a source and a drain on a substrate, and a stack of n vertically separated channel nanowires isolated from the substrate and connecting the source and the drain this article.

TL;DR: The realization of ordered, uniform, array-based In0.53Ga0.47As pillars with diameters as small as 200 nm using the damage-free metal-assisted chemical etching ( MacEtch) technology combined with the post-MacEtch digital etching smoothing is demonstrated.