Y
Yiyang Jiang
Researcher at Chinese Academy of Sciences
Publications - 7
Citations - 104
Yiyang Jiang is an academic researcher from Chinese Academy of Sciences. The author has contributed to research in topics: Computer science & Latency (audio). The author has an hindex of 1, co-authored 2 publications receiving 43 citations.
Papers
More filters
Journal ArticleDOI
MoTe2 p-n Homojunctions Defined by Ferroelectric Polarization.
Guangjian Wu,Guangjian Wu,Xudong Wang,Yan Chen,Shuaiqin Wu,Binmin Wu,Yiyang Jiang,Hong Shen,Tie Lin,Qi Liu,Xinran Wang,Peng Zhou,Shan-Tao Zhang,Weida Hu,Xiangjian Meng,Junhao Chu,Jianlu Wang +16 more
TL;DR: Efficient carrier modulation in ambipolar molybdenum telluride (MoTe2) to form a p-n homojunction at the domain wall is demonstrated and presents an obvious short-wavelength infrared photoresponse at room temperature.
Journal ArticleDOI
Effect of archwire plane and archwire size on anterior teeth movement in sliding mechanics in customized labial orthodontics: a 3D finite element study
TL;DR: A 3D finite element method was applied to simulate anterior teeth retraction with and without miniscrew and power arm, and the initial displacements and pressure stresses of periodontal tissue in anterior teeth were calculated after the teeth were applied with retraction forces with different archwire planes and archwire sizes as mentioned in this paper .
Journal ArticleDOI
Multimode Signal Processor Unit Based on the Ambipolar WSe2-Cr Schottky Junction.
Yan Chen,Chong Yin,Chong Yin,Xudong Wang,Yiyang Jiang,Haoliang Wang,Binmin Wu,Hong Shen,Tie Lin,Weida Hu,Xiangjian Meng,Piyi Du,Junhao Chu,Zongrong Wang,Jianlu Wang +14 more
TL;DR: The highly tunable Schottky junction working as a multimode signal processor unit has great potential in future optoelectronic-integrated chips.
Journal ArticleDOI
Optimal read voltages decision scheme eliminating read retry operations for 3D NAND flash memories
TL;DR: In this article , the authors proposed an ORVs decision scheme without specific read retry operations (ORVD-WRRO) to eliminate the read operations required by read retries and thus decrease the read latency.
Journal ArticleDOI
Read latency decrease schemes based on check node error rate for 3D NAND flash memories
Qianhui Li,Qi Wang,Liuqing Yang,Yiyang Jiang,Jing He,Xiaolin Yu,Qianqian Wang,Ken Chen,Xianliang Wang,Zongliang Huo +9 more
TL;DR: In this article , a check node error rate (CNER) based adaptive-step valley search algorithm for read retry operations to decrease read latency is proposed. But, the proposed algorithm is not suitable for data recovery.