In this paper, we present a comprehensive reviewand discussion of the state-of-the-art device technology and application development of GaN-on-Si power electronics. Several device technologies for realizing normally off operation that is highly desirable for power switching applications are presented. In addition, the examples of circuit applications that can greatly benefit from the superior performance of GaN power devices are demonstrated. Comparisonwith other competingpower device technology, such as Si superjunction-MOSFET and SiC MOSFET, is also presented and analyzed. Critical issues for commercialization of GaN-on-Si power devices are discussed with regard to cost, reliability, and ease of use.

GaN-on-Si Power Technology: Devices and Applications

Wide-band-gap GaN and Ga-rich InGaN alloys, with energy gaps covering the blue and near-ultraviolet parts of the electromagnetic spectrum, are one group of the dominant materials for solid state lighting and lasing technologies and consequently, have been studied very well. Much less effort has been devoted to InN and In-rich InGaN alloys. A major breakthrough in 2002, stemming from much improved quality of InN films grown using molecular beam epitaxy, resulted in the bandgap of InN being revised from 1.9 eV to a much narrower value of 0.64 eV. This finding triggered a worldwide research thrust into the area of narrow-band-gap group-III nitrides. The low value of the InN bandgap provides a basis for a consistent description of the electronic structure of InGaN and InAlN alloys with all compositions. It extends the fundamental bandgap of the group III-nitride alloy system over a wider spectral region, ranging from the near infrared at ∼1.9 μm (0.64 eV for InN) to the ultraviolet at ∼0.36 μm (3.4 eV for GaN...

When group-III nitrides go infrared: New properties and perspectives

Gallium nitride (GaN) is a compound semiconductor that has tremendous potential to facilitate economic growth in a semiconductor industry that is silicon-based and currently faced with diminishing returns of performance versus cost of investment. At a material level, its high electric field strength and electron mobility have already shown tremendous potential for high frequency communications and photonic applications. Advances in growth on commercially viable large area substrates are now at the point where power conversion applications of GaN are at the cusp of commercialisation. The future for building on the work described here in ways driven by specific challenges emerging from entirely new markets and applications is very exciting. This collection of GaN technology developments is therefore not itself a road map but a valuable collection of global state-of-the-art GaN research that will inform the next phase of the technology as market driven requirements evolve. First generation production devices are igniting large new markets and applications that can only be achieved using the advantages of higher speed, low specific resistivity and low saturation switching transistors. Major investments are being made by industrial companies in a wide variety of markets exploring the use of the technology in new circuit topologies, packaging solutions and system architectures that are required to achieve and optimise the system advantages offered by GaN transistors. It is this momentum that will drive priorities for the next stages of device research gathered here.

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The 2018 GaN power electronics roadmap

Interface engineering is a key strategy to deal with the two-dimensional (2D)/three-dimensional (3D) hybrid heterostructure, since the properties of this atomic-layer-thick 2D material can easily be impacted by the substrate environment. In this work, the structural, electronic, and optical properties of the 2D/3D heterostructure of monolayer MoS2 on wurtzite GaN surface without and with nitridation interfacial layer are systematically investigated by first-principles calculation and experimental analysis. The nitridation interfacial layer can be introduced into the 2D/3D heterostructure by remote N2 plasma treatment to GaN sample surface prior to stacking monolayer MoS2 on top. The calculation results reveal that the 2D/3D integrated heterostructure is energetically favorable with a negative formation energy. Both interfaces demonstrate indirect band gap, which is a benefit for longer lifetime of the photoexcited carriers. Meanwhile, the conduction band edge and valence band edge of the MoS2 side increas...

Interface Engineering of Monolayer MoS2/GaN Hybrid Heterostructure: Modified Band Alignment for Photocatalytic Water Splitting Application by Nitridation Treatment.

As complementary metal-oxide-semiconductor (CMOS) technologies are scaled down into the nanometer range, a number of major nonidealities must be addressed and overcome to achieve a successful analog and physical circuit design. The nature of these nonidealities has been well reported in the technical literature. They include hot carrier injection and time-dependent dielectric breakdown effects limiting supply voltage, stress and lithographic effects limiting matching accuracy, electromigration effects limiting conductor lifetime, leakage and mobility effects limiting device performance, and chip power dissipation limits driving individual circuits to be more energy-efficient. The lack of analog design and simulation tools available to address these problems has become the focus of a significant effort with the electronic design automation industry. Postlayout simulation tools are not useful during the design phase, while technology computer-aided design physical simulation tools are slow and not in common use by analog circuit designers. In the nanoscale era of analog CMOS design, an understanding of the physical factors affecting circuit reliability and performance, as well as methods of mitigating or overcoming them, is becoming increasingly important. The first part of the paper presents factors affecting device matching, including those relating to single devices as well as local and long-distance matching effects. Several reliability effects are discussed, including physical design limitations projected for future downscaling. In some cases, it may be helpful to exceed foundry-specified drain-source voltage limits by a few hundred millivolts. Models are presented for achieving this, which include the dependence on the shape of the output waveform. The condition Vsb > 0 is required for cascode circuit configurations. The role of other terminal voltages is discussed, as Vsb > 0 increases both hot and cold carrier damage effects in highly scaled devices. The second part of the paper focuses on trends in device characteristics and how they influence the design of nanoscale analog CMOS circuits. A number of circuit design techniques employed to address the major nonidealities of nanoscale CMOS technologies are discussed. Examples include techniques for establishing on-chip accurate and temperature-insensitive bias currents, digital calibration of analog circuits, and the design of regulator and high-voltage circuits. Achieving high energy efficiency in ICs capable of accommodating 109 devices is becoming critically important. This paper also presents a survey of the evolution of figure of merit for analog-to-digital converters.

Analog Circuit Design in Nanoscale CMOS Technologies

We report an in situ low-damage pre-gate treatment technology in an atomic layer deposition (ALD) system prior to the ALD- Al2O3 deposition, to realize high-quality Al2O3/III-nitride (III-N) interface. The technology effectively removes the poor quality native oxide on the III-N surface while forming an ultrathin monocrystal-like nitridation interlayer (NIL) between Al2O3 and III-N surface. With the pre-gate treatment technology, high-performance Al2O3(NIL)/GaN/AlGaN/GaN metal-insulator-semiconductor high-electron-mobility transistors are demonstrated, exhibiting well-behaved electrical characteristics including suppressed gate leakage current, a small subthreshold slope of ~64 mV/dec, and a small hysteresis of ~0.09 V.

High-Quality Interface in ${\rm Al}_{2}{\rm O}_{3}/{\rm GaN}/{\rm GaN}/{\rm AlGaN}/{\rm GaN}$ MIS Structures With In Situ Pre-Gate Plasma Nitridation

In this letter, a selective Si diffusion approach is proposed to improve both the forward and reverse characteristics of AlGaN/GaN Schottky barrier diodes on Si substrates. The Si diffusion layer forms a dual Schottky barrier anode structure, which results in a low Schottky barrier portion to reduce the onset voltage VON from 1.3 to 1.0 V (23%). In the same process step, the selectively diffused Si is adopted in the cathode to reduce the ohmic contact resistance RC and improve the breakdown voltage VBK. A low RC of 0.21 Ω·mm and enhanced VBK up to 20% (from 1250 to 1500 V) are demonstrated, which can be attributed to the alleviated electric-field peaks around the alloy spikes beneath the ohmic contact.

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AlGaN/GaN Schottky Barrier Diodes on Silicon Substrates With Selective Si Diffusion for Low Onset Voltage and High Reverse Blocking

With an in situ low-damage NH3-Ar-N2 plasma pre-gate treatment, a high-quality Al2O3/GaN-cap interface has been obtained in the Al2O3/GaN/AlGaN/GaN MIS-structures. Frequency- and temperature-dependent C-V characterization techniques were developed to map the interface trap density (Dit) at the dielectric/III-nitride interface, whereby a low Dit of ~1012-1013 cm-2eV-1 in the Al2O3/GaN/AlGaN/GaN MIS-structures was extracted. The mechanism for the high-quality interface was validated to be effective removal of native oxide and the subsequent formation of a monocrystal-like nitridation inter-layer on the GaN surface. Both Dit mapping and the pre-gate treatment techniques are of significance for the improvement of III-nitride MIS-HEMTs.

Mapping of interface traps in high-performance Al 2 O 3 /AlGaN/GaN MIS-heterostructures using frequency- and temperature-dependent C-V techniques

In this letter, we propose using an oxide-filled isolation structure followed by N2/H2 postgate annealing to reduce the leakage current in AlGaN/GaN HEMTs. An off-state drain leakage current that is smaller than 10-9 A/mm (minimum 5.1 × 10-10 A/mm) can be achieved, and a gate leakage current in the range of 7.8 ×10-10 to 9.2 × 10-11A/mm (V GS from -10 to 0 V and V DS = 10 V) is obtained. The substantially reduced leakage current results in an excellent on/off current ratio that is up to 1.5 × 108. An improved flicker noise characteristic is also observed in the oxide-filled devices compared with that in the traditional mesa-isolated GaN HEMTs.

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AlGaN/GaN HEMTs With Low Leakage Current and High On/Off Current Ratio

This paper explores the next stage of GaN power devices with 2-level integration of peripheral low voltage active and passive devices The 1st level consists of protection/control/driving circuits, which potentially improves the performance and overcomes the challenges to the power devices The 2nd level integration has high-low side on-chip integration on a 100V technology platform The challenge of channel modulation due to substrate bias sharing is effectively eliminated by the invented new scheme The system efficiency of DC-DC buck converter using such scheme is enhanced with lower on-state resistance and good stability

Yu-Syuan Lin

Papers

High-Quality Interface in ${\rm Al}_{2}{\rm O}_{3}/{\rm GaN}/{\rm GaN}/{\rm AlGaN}/{\rm GaN}$ MIS Structures With In Situ Pre-Gate Plasma Nitridation

AlGaN/GaN Schottky Barrier Diodes on Silicon Substrates With Selective Si Diffusion for Low Onset Voltage and High Reverse Blocking

Mapping of interface traps in high-performance Al 2 O 3 /AlGaN/GaN MIS-heterostructures using frequency- and temperature-dependent C-V techniques

AlGaN/GaN HEMTs With Low Leakage Current and High On/Off Current Ratio

Smart GaN platform: Performance & challenges