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Yuan Xie
Researcher at University of California, Santa Barbara
Publications - 794
Citations - 32484
Yuan Xie is an academic researcher from University of California, Santa Barbara. The author has contributed to research in topics: Computer science & Cache. The author has an hindex of 76, co-authored 739 publications receiving 24155 citations. Previous affiliations of Yuan Xie include Pennsylvania State University & Foundation University, Islamabad.
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PRIME: a novel processing-in-memory architecture for neural network computation in ReRAM-based main memory
TL;DR: This work proposes a novel PIM architecture, called PRIME, to accelerate NN applications in ReRAM based main memory, and distinguishes itself from prior work on NN acceleration, with significant performance improvement and energy saving.
Journal ArticleDOI
NVSim: A Circuit-Level Performance, Energy, and Area Model for Emerging Nonvolatile Memory
TL;DR: NVSim is developed, a circuit-level model for NVM performance, energy, and area estimation, which supports various NVM technologies, including STT-RAM, PCRAM, ReRAM, and legacy NAND Flash and is expected to help boost architecture-level NVM-related studies.
Journal ArticleDOI
Towards artificial general intelligence with hybrid Tianjic chip architecture.
Jing Pei,Lei Deng,Sen Song,Sen Song,Mingguo Zhao,Youhui Zhang,Shuang Wu,Guanrui Wang,Zhe Zou,Zhenzhi Wu,Wei He,Feng Chen,Ning Deng,Si Wu,Yu Wang,Yujie Wu,Z. Yang,Cheng Ma,Guoqi Li,Wentao Han,Huanglong Li,Huaqiang Wu,Rong Zhao,Yuan Xie,Luping Shi +24 more
TL;DR: The Tianjic chip is presented, which integrates neuroscience-oriented and computer-science-oriented approaches to artificial general intelligence to provide a hybrid, synergistic platform and is expected to stimulate AGI development by paving the way to more generalized hardware platforms.
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Model Compression and Hardware Acceleration for Neural Networks: A Comprehensive Survey
TL;DR: This article reviews the mainstream compression approaches such as compact model, tensor decomposition, data quantization, and network sparsification, and answers the question of how to leverage these methods in the design of neural network accelerators and present the state-of-the-art hardware architectures.
Proceedings ArticleDOI
A novel architecture of the 3D stacked MRAM L2 cache for CMPs
TL;DR: This paper stacks MRAM-based L2 caches directly atop CMPs and compares it against SRAM counterparts in terms of performance and energy, and proposes two architectural techniques: read-preemptive write buffer and SRAM-MRAM hybrid L2 cache.