Probability Distributions.- Linear Models for Regression.- Linear Models for Classification.- Neural Networks.- Kernel Methods.- Sparse Kernel Machines.- Graphical Models.- Mixture Models and EM.- Approximate Inference.- Sampling Methods.- Continuous Latent Variables.- Sequential Data.- Combining Models.

Pattern Recognition and Machine Learning

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Design Of Analog Cmos Integrated Circuits

The rapid increase in information in the big-data era calls for changes to information-processing paradigms, which, in turn, demand new circuit-building blocks to overcome the decreasing cost-effectiveness of transistor scaling and the intrinsic inefficiency of using transistors in non-von Neumann computing architectures. Accordingly, resistive switching materials (RSMs) based on different physical principles have emerged for memories that could enable energy-efficient and area-efficient in-memory computing. In this Review, we survey the four physical mechanisms that lead to such resistive switching: redox reactions, phase transitions, spin-polarized tunnelling and ferroelectric polarization. We discuss how these mechanisms equip RSMs with desirable properties for representation capability, switching speed and energy, reliability and device density. These properties are the key enablers of processing-in-memory platforms, with applications ranging from neuromorphic computing and general-purpose memcomputing to cybersecurity. Finally, we examine the device requirements for such systems based on RSMs and provide suggestions to address challenges in materials engineering, device optimization, system integration and algorithm design. Resistive switching materials enable novel, in-memory information processing, which may resolve the von Neumann bottleneck. This Review focuses on how the switching mechanisms and the resultant electrical properties lead to various computing applications.

Resistive switching materials for information processing

A nociceptor is a critical and special receptor of a sensory neuron that is able to detect noxious stimulus and provide a rapid warning to the central nervous system to start the motor response in the human body and humanoid robotics. It differs from other common sensory receptors with its key features and functions, including the “no adaptation” and “sensitization” phenomena. In this study, we propose and experimentally demonstrate an artificial nociceptor based on a diffusive memristor with critical dynamics for the first time. Using this artificial nociceptor, we further built an artificial sensory alarm system to experimentally demonstrate the feasibility and simplicity of integrating such novel artificial nociceptor devices in artificial intelligence systems, such as humanoid robots. The development of humanoid robots with artificial intelligence calls for smart solutions for tactile sensing systems that respond to dynamic changes in the environment. Here, Yoon et al. emulate non-adaption and sensitization function of a nociceptor—a sensory neuron—using diffusive oxide-based memristors.

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An artificial nociceptor based on a diffusive memristor.

This survey covers research into mixed criticality systems that has been published since Vestal’s seminal paper in 2007, up until the end of 2016. The survey is organised along the lines of the major research areas within this topic. These include single processor analysis (including fixed priority and Earliest Deadline First (EDF) scheduling, shared resources, and static and synchronous scheduling), multiprocessor analysis, realistic models, and systems issues. The survey also explores the relationship between research into mixed criticality systems and other topics such as hard and soft time constraints, fault tolerant scheduling, hierarchical scheduling, cyber physical systems, probabilistic real-time systems, and industrial safety standards.

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A Survey of Research into Mixed Criticality Systems

Memristors are considered among the most promising future building blocks of next-generation digital systems. This paper focuses on specific ways to implement logic and arithmetic unit using memristors. In particular, we present a set of complementary resistive switching (CRS)-based stateful logic operations that use material implication to provide the basic logic functionalities needed to realize logic circuits. The proposed solution benefits from the exponential reduction in sneak path current in crossbar implemented logic. This paper also presents a closed-form expression for sneak current and analyzes the impact of device variation on the behavior of the proposed logic blocks. Our technique, as other similar techniques proposed in the literature, requires several sequential steps to perform the computation. However, in this paper, we show that only three steps are required for implementing N input nand gate, whereas previously proposed memristor-based stateful logic needs N + 1 steps. We validated the effectiveness of our solution through cadence spectre circuit simulator on a number of logic circuits. Finally, we extended this approach for arithmetic circuits with an 8-bit adder and a 4-bit multiplier.

Complementary Resistive Switch-Based Arithmetic Logic Implementations Using Material Implication

Memristor is an exciting new addition to the repertoire of fundamental circuit elements. Alternatives to many security protocols originally employing traditional mathematical cryptography involve novel hardware security primitives, such as Physically Unclonable Functions (PUFs). In this article, we propose a novel hybrid memristor-CMOS PUF circuit and demonstrate its suitability through extensive simulations of environmental and process variation effects. The proposed PUF circuit has substantially less hardware overhead than previously proposed memristor-based PUF circuits while being inherently resistant to machine learning-based modeling attacks because of challenge-dependent delays of the memristor stages. The proposed PUF can be conveniently used in many security applications and protocols based on hardware-intrinsic security.

A Novel Memristor-Based Hardware Security Primitive

A novel memristor based physically unclonable function

Resistive memory, also known as memristor, is recently emerging as a potential successor to traditional charge-based memories. However, the nanoscale features of these devices introduce challenges in modeling and simulation. In this paper, we propose a novel Verilog-A based complementary resistive switch memory model for effective simulation and analysis. Our proposed model captures desired nonlinear characteristics using voltage based state control as opposed to recently proposed current based state control. We demonstrate that such state control has advantages for our proposed CRS model based crossbar arrays in terms of symmetric ON/OFF voltages and significantly reduced sneak path currents with high noise margin compared to traditional memristor based architectures. Moreover, to validate the effectiveness of our Verilog-A based model we carry out extensive simulations and analyses for different crossbar array architectures using traditional EDA tools.

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Verilog-A Based Effective Complementary Resistive Switch Model for Simulations and Analysis

Recent trends in emerging nonvolatile memory systems necessitate efficient read/write (R/W) schemes Efficient solutions with zero sneak path current, nondestructive R/W operations, minimum area and low power are some of the key requirements Toward this end, we propose a novel crossbar memory scheme using a configuration row of cells for assisting R/W operations The proposed write scheme minimizes the overall power consumption compared to the previously proposed write schemes and reduces the state drift problem We also propose two read schemes, namely, assisted-restoring and self-resetting read In assisted-restoring scheme, we use the configuration cells which are used in the write scheme, whereas we implement additional circuitry for self-reset which addresses the problem of destructive read Moreover, by formulating an analytical model of R/W operation, we compare the various schemes The overhead for the proposed assisted-restoring write/read scheme is an extra redundant row for the given crossbar array For a typical array size of $200\times 200$ the area overhead is about $05\%$ , however, there is a 4X improvement in power consumption compared to the recently proposed write schemes Quantitative analysis of the proposed scheme is analyzed by using simulation and analytical models

Yuanfan Yang

Papers

Complementary Resistive Switch-Based Arithmetic Logic Implementations Using Material Implication

A Novel Memristor-Based Hardware Security Primitive

A novel memristor based physically unclonable function

Verilog-A Based Effective Complementary Resistive Switch Model for Simulations and Analysis

Novel Complementary Resistive Switch Crossbar Memory Write and Read Schemes