Z
Zhijiong Luo
Researcher at IBM
Publications - 55
Citations - 1018
Zhijiong Luo is an academic researcher from IBM. The author has contributed to research in topics: Layer (electronics) & Field-effect transistor. The author has an hindex of 16, co-authored 55 publications receiving 1016 citations. Previous affiliations of Zhijiong Luo include Chartered Semiconductor Manufacturing.
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Patent
Opto-thermal annealing methods for forming metal gate and fully silicided gate field effect transistors
Scott D. Allen,Cyril Cabral,Kevin K. Dezfulian,Sunfei Fang,Brian J. Greene,Rajarao Jammy,Christian Lavoie,Zhijiong Luo,Hung Ng,Chun-Yung Sung,C. Wann,Huilong Zhu +11 more
TL;DR: In this paper, an opto-thermal annealing method for forming a field effect transistor uses a reflective metal gate so that electrical properties of the metal gate and also interface between the gate and a gate dielectric are not compromised.
Patent
Self-aligned and extended inter-well isolation structure
TL;DR: In this paper, a pedestal is formed out of the pad layer such that two edges of the pedestal coincide with a border of the wells as implanted, and an extended pedestal was formed over the pedestals by depositing a conformal dielectric layer.
Proceedings ArticleDOI
High performance and low power transistors integrated in 65nm bulk CMOS technology
Zhijiong Luo,An L. Steegen,Manfred Eller,Randy W. Mann,Christopher V. Baiocco,Phung T. Nguyen,L. Kim,Mark Hoinkis,Victor Ku,V. Klee,F.F. Jamin,P. Wrschka,Padraic Shafer,Wenhe Lin,Sunfei Fang,A. Ajmera,W. L. Tan,D.-G. Park,R. Mo,Jenny Lian,Dirk Vietzke,C. Coppock,A. Vayshenker,Terence B. Hook,Victor Chan,K. Kim,Andy Cowley,Seong-Dong Kim,Erdem Kaltalioglu,B. Zhang,S. Marokkey,Y. H. Lin,K-C. Lee,Huilong Zhu,M. Weybright,Rajesh Rengarajan,JiYeon Ku,T. Schiml,J. Sudijono,I. Yang,C. Wann +40 more
TL;DR: In this article, the authors report a cutting-edge 65nm CMOS technology featuring high performance and low power CMOS devices for both general and low-power applications for both low power and high performance applications.
Patent
Method for forming retrograded well for MOSFET
TL;DR: In this paper, a method of forming an electrical device is provided that includes forming at least one semiconductor device on a first semiconductor layer of the SOI substrate, which is formed by implanting dopant through the substantially exposed surface.
Patent
Structure and method to form multilayer embedded stressors
TL;DR: In this article, a multilayer embedded stressor having a graded dopant profile for use in a semiconductor structure for inducing strain on a device channel region is provided, which is formed within areas of semiconductor structures in which source/drain regions are typically located.