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Sunfei Fang
Researcher at IBM
Publications - 22
Citations - 623
Sunfei Fang is an academic researcher from IBM. The author has contributed to research in topics: Gate oxide & Field-effect transistor. The author has an hindex of 11, co-authored 22 publications receiving 597 citations.
Papers
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Patent
Opto-thermal annealing methods for forming metal gate and fully silicided gate field effect transistors
Scott D. Allen,Cyril Cabral,Kevin K. Dezfulian,Sunfei Fang,Brian J. Greene,Rajarao Jammy,Christian Lavoie,Zhijiong Luo,Hung Ng,Chun-Yung Sung,C. Wann,Huilong Zhu +11 more
TL;DR: In this paper, an opto-thermal annealing method for forming a field effect transistor uses a reflective metal gate so that electrical properties of the metal gate and also interface between the gate and a gate dielectric are not compromised.
Proceedings ArticleDOI
High performance 14nm SOI FinFET CMOS technology with 0.0174µm 2 embedded DRAM and 15 levels of Cu metallization
C-H. Lin,Brian J. Greene,Shreesh Narasimha,J. Cai,A. Bryant,Carl J. Radens,Vijay Narayanan,Barry Linder,Herbert L. Ho,A. Aiyar,E. Alptekin,J-J. An,Michael V. Aquilino,Ruqiang Bao,V. Basker,Nicolas Breil,MaryJane Brodsky,William Y. Chang,Clevenger Leigh Anne H,Dureseti Chidambarrao,Cathryn Christiansen,D. Conklin,C. DeWan,H. Dong,L. Economikos,Bernard A. Engel,Sunfei Fang,D. Ferrer,A. Friedman,Allen H. Gabor,Fernando Guarin,Ximeng Guan,M. Hasanuzzaman,J. Hong,D. Hoyos,Basanth Jagannathan,S. Jain,S.-J. Jeng,J. Johnson,B. Kannan,Y. Ke,Babar A. Khan,Byeong Y. Kim,Siyuranga O. Koswatta,Amit Kumar,T. Kwon,Unoh Kwon,L. Lanzerotti,H-K Lee,W-H. Lee,A. Levesque,Wai-kin Li,Zhengwen Li,Wei Liu,S. Mahajan,Kevin McStay,Hasan M. Nayfeh,W. Nicoll,G. Northrop,A. Ogino,Chengwen Pei,S. Polvino,Ravikumar Ramachandran,Z. Ren,Robert R. Robison,Saraf Iqbal Rashid,Viraj Y. Sardesai,S. Saudari,Dominic J. Schepis,Christopher D. Sheraw,Shariq Siddiqui,Liyang Song,Kenneth J. Stein,C. Tran,Henry K. Utomo,Reinaldo A. Vega,Geng Wang,Han Wang,W. Wang,X. Wang,D. Wehelle-Gamage,E. Woodard,Yongan Xu,Y. Yang,N. Zhan,Kai Zhao,C. Zhu,K. Boyd,E. Engbrecht,K. Henson,E. Kaste,Siddarth A. Krishnan,Edward P. Maciejewski,Huiling Shang,Noah Zamdmer,R. Divakaruni,J. Rice,Scott R. Stiffler,Paul D. Agnello +98 more
TL;DR: In this article, the authors present a fully integrated 14nm CMOS technology featuring fin-FET architecture on an SOI substrate for a diverse set of SoC applications including HP server microprocessors and LP ASICs.
Proceedings ArticleDOI
High performance and low power transistors integrated in 65nm bulk CMOS technology
Zhijiong Luo,An L. Steegen,Manfred Eller,Randy W. Mann,Christopher V. Baiocco,Phung T. Nguyen,L. Kim,Mark Hoinkis,Victor Ku,V. Klee,F.F. Jamin,P. Wrschka,Padraic Shafer,Wenhe Lin,Sunfei Fang,A. Ajmera,W. L. Tan,D.-G. Park,R. Mo,Jenny Lian,Dirk Vietzke,C. Coppock,A. Vayshenker,Terence B. Hook,Victor Chan,K. Kim,Andy Cowley,Seong-Dong Kim,Erdem Kaltalioglu,B. Zhang,S. Marokkey,Y. H. Lin,K-C. Lee,Huilong Zhu,M. Weybright,Rajesh Rengarajan,JiYeon Ku,T. Schiml,J. Sudijono,I. Yang,C. Wann +40 more
TL;DR: In this article, the authors report a cutting-edge 65nm CMOS technology featuring high performance and low power CMOS devices for both general and low-power applications for both low power and high performance applications.
Patent
Metal gate mosfet by full semiconductor metal alloy conversion
TL;DR: In this article, a metal-containing layer (56) was proposed to convert the semiconductor layer (20) to a semiconductor metal alloy in a second MOSFET type region (30).
Proceedings ArticleDOI
Advanced gate stacks with fully silicided (FUSI) gates and high-/spl kappa/ dielectrics: enhanced performance at reduced gate leakage
Evgeni Gusev,Cyril Cabral,B.P. Under,Young-Hee Kim,Kingsuk Maitra,Hasan M. Nayfeh,R. Amos,Glenn A. Biery,Nestor A. Bojarczuk,Alessandro C. Callegari,Roy A. Carruthers,Stephan A. Cohen,Matthew Copel,Sunfei Fang,Martin M. Frank,Supratik Guha,Michael A. Gribelyuk,Paul C. Jamison,Rajarao Jammy,Meikei Ieong,J. Kedzierski,P. Kozlowski,K. Ku,Dianne L. Lacey,D. LaTulipe,Vijay Narayanan,H. Ng,Phung T. Nguyen,J. Newbury,Vamsi Paruchuri,Rajesh Rengarajan,Ghavam G. Shahidi,An L. Steegen,Michelle L. Steen,Sufi Zafar,Y. Zhang +35 more
TL;DR: In this paper, FUSI/HfSi/sub x/O/sub y/ gate stacks offer both significant gate leakage reduction (due to high/spl kappa/) and drive current improvement at T/sub inv/ /spl sim/ 2 nm.