Atomic layer deposition: an overview.

A common feature of the single-walled carbon-nanotube field-effect transistors fabricated to date has been the presence of a Schottky barrier at the nanotube–metal junctions1,2,3. These energy barriers severely limit transistor conductance in the ‘ON’ state, and reduce the current delivery capability—a key determinant of device performance. Here we show that contacting semiconducting single-walled nanotubes by palladium, a noble metal with high work function and good wetting interactions with nanotubes, greatly reduces or eliminates the barriers for transport through the valence band of nanotubes. In situ modification of the electrode work function by hydrogen is carried out to shed light on the nature of the contacts. With Pd contacts, the ‘ON’ states of semiconducting nanotubes can behave like ohmically contacted ballistic metallic tubes, exhibiting room-temperature conductance near the ballistic transport limit of 4e2/h (refs 4–6), high current-carrying capability (∼25 µA per tube), and Fabry–Perot interferences5 at low temperatures. Under high voltage operation, the current saturation appears to be set by backscattering of the charge carriers by optical phonons. High-performance ballistic nanotube field-effect transistors with zero or slightly negative Schottky barriers are thus realized.

Ballistic carbon nanotube field-effect transistors

We present the science and technology roadmap for graphene, related two-dimensional crystals, and hybrid systems, targeting an evolution in technology, that might lead to impacts and benefits reaching into most areas of society. This roadmap was developed within the framework of the European Graphene Flagship and outlines the main targets and research areas as best understood at the start of this ambitious project. We provide an overview of the key aspects of graphene and related materials (GRMs), ranging from fundamental research challenges to a variety of applications in a large number of sectors, highlighting the steps necessary to take GRMs from a state of raw potential to a point where they might revolutionize multiple industries. We also define an extensive list of acronyms in an effort to standardize the nomenclature in this emerging field.

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Science and technology roadmap for graphene, related two-dimensional crystals, and hybrid systems

Individual graphene oxide sheets subjected to chemical reduction were electrically characterized as a function of temperature and external electric fields. The fully reduced monolayers exhibited conductivities ranging between 0.05 and 2 S/cm and field effect mobilities of 2−200 cm2/Vs at room temperature. Temperature-dependent electrical measurements and Raman spectroscopic investigations suggest that charge transport occurs via variable range hopping between intact graphene islands with sizes on the order of several nanometers. Furthermore, the comparative study of multilayered sheets revealed that the conductivity of the undermost layer is reduced by a factor of more than 2 as a consequence of the interaction with the Si/SiO2 substrate.

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Electronic Transport Properties of Individual Chemically Reduced Graphene Oxide Sheets

The semiconductor industry has been able to improve the performance of electronic systems for more than four decades by making ever-smaller devices. However, this approach will soon encounter both scientific and technical limits, which is why the industry is exploring a number of alternative device technologies. Here we review the progress that has been made with carbon nanotubes and, more recently, graphene layers and nanoribbons. Field-effect transistors based on semiconductor nanotubes and graphene nanoribbons have already been demonstrated, and metallic nanotubes could be used as high-performance interconnects. Moreover, owing to the excellent optical properties of nanotubes it could be possible to make both electronic and optoelectronic devices from the same material.

Carbon-based electronics.

Ambipolar electrical transport is reported in single-wall carbon nanotube (SWNT) field-effect transistors. In particular, the properties of SWNT junctions to TiC are discussed in detail. The carbide-nanotube junctions are abrupt and robust. In contrast to planar junctions, these contacts present low resistance for the injection of both $p$- and $n$-type carriers---the apparent barrier height of the junction is modified by the gate field. Thus SWNTs offer the novel possibility of ambipolar Ohmic contacts.

Ambipolar electrical transport in semiconducting single-wall carbon nanotubes.

Towards implementation of a nickel silicide process for CMOS technologies

A systematic study of the thermally induced reaction of 20 transition metals (Ti, Zr, Hf, V, Nb, Ta, Cr, Mo, W, Mn, Re, Fe, Ru, Co, Rh, Ir, Ni, Pd, Pt, and Cu) with Ge substrates was carried out in order to identify appropriate contact materials in Ge-based microelectronic circuits. Thin metal films, nominally 30nm thick, were sputter deposited on both amorphous Ge and crystalline Ge(001). Metal-Ge reactions were monitored in situ during ramp anneals at 3°Cs−1 in an atmosphere of purified He using time-resolved x-ray diffraction, diffuse light scattering, and resistance measurements. These analyses allowed the determination of the phase formation sequence for each metal-Ge system and the identification of the most promising candidates—in terms of sheet resistance and surface roughness—for their use as first level interconnections in microelectronic circuits. A first group of metals (Ti, Zr, Hf, V, Nb, and Ta) reacted with Ge only at temperatures well above 450°C and was prone to oxidation. Another set (Cr...

Thin film reaction of transition metals with germanium

A complementary metal oxide semiconductor (CMOS) device, e.g., a field effect transistor (FET), that includes at least one one-dimensional nanostructure that is typically a carbon-based nanomaterial, as the device channel, and a metal carbide contact that is self-aligned with the gate region of the device is described. The present invention also provides a method of fabricating such a CMOS device.

Self-aligned process for nanotube/nanowire FETs

Metal-gate FinFET and FDSOI devices were fabricated using total gate silicidation. Devices satisfy the following metal-gate technology requirements: ideal mobility, low gate leakage, high transconductance, competitive I/sub on//I/sub off/, and adjustable V/sub t/. Six silicide gate materials are presented, as well as two silicide workfunction engineering methods.

Christian Lavoie

Papers

Ambipolar electrical transport in semiconducting single-wall carbon nanotubes.

Towards implementation of a nickel silicide process for CMOS technologies

Thin film reaction of transition metals with germanium

Self-aligned process for nanotube/nanowire FETs

Metal-gate FinFET and fully-depleted SOI devices using total gate silicidation