D
D.-G. Park
Researcher at IBM
Publications - 25
Citations - 520
D.-G. Park is an academic researcher from IBM. The author has contributed to research in topics: CMOS & Metal gate. The author has an hindex of 14, co-authored 24 publications receiving 495 citations.
Papers
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Proceedings ArticleDOI
High performance and low power transistors integrated in 65nm bulk CMOS technology
Zhijiong Luo,An L. Steegen,Manfred Eller,Randy W. Mann,Christopher V. Baiocco,Phung T. Nguyen,L. Kim,Mark Hoinkis,Victor Ku,V. Klee,F.F. Jamin,P. Wrschka,Padraic Shafer,Wenhe Lin,Sunfei Fang,A. Ajmera,W. L. Tan,D.-G. Park,R. Mo,Jenny Lian,Dirk Vietzke,C. Coppock,A. Vayshenker,Terence B. Hook,Victor Chan,K. Kim,Andy Cowley,Seong-Dong Kim,Erdem Kaltalioglu,B. Zhang,S. Marokkey,Y. H. Lin,K-C. Lee,Huilong Zhu,M. Weybright,Rajesh Rengarajan,JiYeon Ku,T. Schiml,J. Sudijono,I. Yang,C. Wann +40 more
TL;DR: In this article, the authors report a cutting-edge 65nm CMOS technology featuring high performance and low power CMOS devices for both general and low-power applications for both low power and high performance applications.
Patent
Soi structures including a buried boron nitride dielectric
Robert H. Dennard,Alfred Grill,Effendi Leobandung,Deborah A. Neumayer,D.-G. Park,Ghavam G. Shahidi,Leathen Shi +6 more
TL;DR: Boron nitride has a dielectric constant and thermal expansion coefficient close to silicon dioxide as mentioned in this paper, and has a wet and dry etch resistance that is much better than silicon dioxide.
Proceedings Article
High performance 32nm SOI CMOS with high-k/metal gate and 0.149µm 2 SRAM and ultra low-k back end with eleven levels of copper
Brian J. Greene,Q. Liang,K. Amarnath,Y. Wang,J. Schaeffer,M. Cai,Yue Liang,S. Saroop,J. Cheng,A. Rotondaro,Shu-Jen Han,R. Mo,K. McStay,S.H. Ku,R. Pal,Mahender Kumar,B. Dirahoui,B. Yang,F. Tamweber,Woo-Hyeong Lee,M. Steigerwalt,H. Weijtmans,Judson R. Holt,L. Black,S. Samavedam,M. Turner,K. Ramani,D. Lee,Michael P. Belyansky,M. Chowdhury,D. Aime,B. Min,H. van Meer,Haizhou Yin,K.K. Chan,M. Angyal,M. Zaleski,O. Ogunsola,C. Child,L. Zhuang,H. Yan,D. Permanaa,Jeffrey W. Sleight,Dechao Guo,S. Mittl,D. Ioannou,Ernest Y. Wu,Michael P. Chudzik,D.-G. Park,D. Brown,Scott Luning,Dan Mocuta,Edward P. Maciejewski,K. Henson,Effendi Leobandung +54 more
TL;DR: In this paper, a 32 nm SOI CMOS technology featuring high-k/metal gate and an SRAM cell size of 0.149 µm2 is presented, enabling performance without the power penalty from gate capacitance.
Proceedings ArticleDOI
Reduction of random telegraph noise in High-к / metal-gate stacks for 22 nm generation FETs
Naoki Tega,Hiroshi Miki,Zhibin Ren,Christopher P. D'Emic,Yu Zhu,David J. Frank,J. Cai,M. Guillorn,D.-G. Park,Wilfried Haensch,Kazuyoshi Torii +10 more
TL;DR: In this paper, the reduction of random telegraph noise (RTN) in high-к / metal gate (HK / MG) stacks incorporated in 22 nm generation FETs was demonstrated.
Proceedings ArticleDOI
High-mobility High-Ge-Content Si 1−x Ge x -OI PMOS FinFETs with fins formed using 3D germanium condensation with Ge fraction up to x∼ 0.7, scaled EOT∼8.5Å and ∼10nm fin width
Pouya Hashemi,T. Ando,Karthik Balakrishnan,John Bruley,Sebastian Engelmann,John A. Ott,Vijay Narayanan,D.-G. Park,R. Mo,Effendi Leobandung +9 more
TL;DR: In this article, the authors demonstrate scaled high-Ge-content (HGC) SiGe-OI finFET with Ge up to 71% using a CMOS-compatible approach.