Cryptographic Hardware and Embedded Systems 

About: Cryptographic Hardware and Embedded Systems is an academic conference. The conference publishes majorly in the area(s): Side channel attack & Cryptography. Over the lifetime, 834 publications have been published by the conference receiving 75634 citations.

Correlation Power Analysis with a Leakage Model

Abstract: A classical model is used for the power consumption of cryptographic devices. It is based on the Hamming distance of the data handled with regard to an unknown but constant reference state. Once validated experimentally it allows an optimal attack to be derived called Correlation Power Analysis. It also explains the defects of former approaches such as Differential Power Analysis.

PRESENT: An Ultra-Lightweight Block Cipher

Abstract: With the establishment of the AES the need for new block ciphers has been greatly diminished; for almost all block cipher applications the AES is an excellent and preferred choice. However, despite recent implementation advances, the AES is not suitable for extremely constrained environments such as RFID tags and sensor networks. In this paper we describe an ultra-lightweight block cipher, present . Both security and hardware efficiency have been equally important during the design of the cipher and at 1570 GE, the hardware requirements for present are competitive with today's leading compact stream ciphers.

Electromagnetic Analysis: Concrete Results

Abstract: Although the possibility of attacking smart-cards by analyzing their electromagnetic power radiation repeatedly appears in research papers, all accessible references evade the essence of reporting conclusive experiments where actual cryptographic algorithms such as des or RSA were successfully attacked This work describes electromagnetic experiments conducted on three different cmos chips, featuring different hardware protections and executing a des, an alleged comp128 and an rsa In all cases the complete key material was successfully retrieved

FPGA Intrinsic PUFs and Their Use for IP Protection

Abstract: In recent years, IP protection of FPGA hardware designs has become a requirement for many IP vendors. In [34], Simpson and Schaumont proposed a fundamentally different approach to IP protection on FPGAs based on the use of Physical Unclonable Functions (PUFs). Their work only assumes the existence of a PUF on the FPGAs without actually proposing a PUF construction. In this paper, we propose new protocols for the IP protection problem on FPGAs and provide the first construction of a PUF intrinsic to current FPGAs based on SRAM memory randomness present on current FPGAs. We analyze SRAM-based PUF statistical properties and investigate the trade offs that can be made when implementing a fuzzy extractor.