FPGA Intrinsic PUFs and Their Use for IP Protection
Jorge Guajardo,Sandeep Kumar,Geert-Jan Schrijen,Pim Tuyls +3 more
- pp 63-80
TLDR
New protocols for the IP protection problem on FPGAs are proposed and the first construction of a PUF intrinsic to current FPGA based on SRAM memory randomness present on current FFPAs is provided.Abstract:
In recent years, IP protection of FPGA hardware designs has become a requirement for many IP vendors. In [34], Simpson and Schaumont proposed a fundamentally different approach to IP protection on FPGAs based on the use of Physical Unclonable Functions (PUFs). Their work only assumes the existence of a PUF on the FPGAs without actually proposing a PUF construction. In this paper, we propose new protocols for the IP protection problem on FPGAs and provide the first construction of a PUF intrinsic to current FPGAs based on SRAM memory randomness present on current FPGAs. We analyze SRAM-based PUF statistical properties and investigate the trade offs that can be made when implementing a fuzzy extractor.read more
Citations
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Journal ArticleDOI
Power-Up SRAM State as an Identifying Fingerprint and Source of True Random Numbers
TL;DR: It is demonstrated that a 512-byte SRAM fingerprint contains sufficient entropy to generate 128-bit true random numbers and that the generated numbers pass the NIST tests for runs, approximate entropy, and block frequency.
Proceedings ArticleDOI
Modeling attacks on physical unclonable functions
TL;DR: In this article, numerical modeling attacks are used to break the security of physical unclonable functions (PUFs) by constructing a computer algorithm which behaves indistinguishably from the original PUF on almost all CRPs.
Journal ArticleDOI
Theory and practice of error control codes
TL;DR: This chapter discusses algorithmics and modular computations, Theory of Codes and Cryptography (3), and the theory and practice of error control codes (3).
Proceedings ArticleDOI
Extended abstract: The butterfly PUF protecting IP on every FPGA
TL;DR: A new PUF structure called the butterfly PUF that can be used on all types of FPGAs is proposed and experimental results showing their identification and key generation capabilities are presented.
References
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