Showing papers presented at "Electrical Design of Advanced Packaging and Systems Symposium in 2013"

Metal-loop effects in wireless power transfer systems analyzed by simulation and theory

Abstract: This study presents wireless power transfer (WPT) from a transmitter coil to a receiver coil (WPT coils) with a metal loop in the vicinity of the coils by simulation and theoretical analysis. Power transfer efficiency S21 of the WPT system is set to have flat top level, pass-band, lower cut-off frequency, and upper cut-off frequency. The lower cut-off frequency of S21 shifts higher when a metal loop is in the vicinity. On the other hand, the upper cut-off frequency of S21 does not shift. The frequency shift of the lower cut-off frequency is proportional to square of the inductive coupling factor between the metal loop and the WPT coils. At frequencies near the upper cut off frequency, the currents on the WPT coils cancel each other to reduce induced current on the metal loop in the vicinity. The electromagnetic interference (EMI) of the WPT system reduces at the frequencies.

Signal transmission loss on printed circuit board in GHz frequency region

Abstract: Higher-speed signal transmission is strongly required on a printed circuit board to handle massive data in electronic systems. So, signal transmission loss of copper wiring on a printed circuit board has been studied First, total signal loss was divided into dielectric loss and conductor loss quantitatively based on electromagnetic theory. In particular, the scattering loss due to surface roughness of copper foil has been examined in detail. And the usefulness of the copper foil with low surface roughness has been demonstrated.

Development of decoupling capacitor embedded interposers using narrow gap chip parts mounting technology with wideband ultralow PDN impedance

Abstract: We have developed a new chip capacitor embedded interposer using a narrow gap chip parts mounting technology. This interposer is expected to reduce power distribution network (PDN) impedance. To investigate the efficacy of the interposer, we have fabricated other various types of capacitor embedded interposer test element group (TEG), such as a generally chip capacitor embedded organic interposer, a thin film capacitor on a silicon interposer using the same design. We evaluated PDN impedance of decoupling capacitor embedded interposers for 3-D integrated LSI system by using a developed ultralow impedance evaluation system. As a result, the chip capacitor embedded interposer using the narrow gap chip parts mounting technology shows a low PDN impedance below 0.1 Ω could be evaluated at the frequency range of up to 10 GHz. This is realized that the interposer shows the comparable level of the PDN impedance as the thin film capacitor embedded silicon interposer. It can be realized that the PDN impedance of the interposer shows below 1/100 compared with a general interposer with embedded the chip capacitor parts of 0603 types.

Mode conversion caused by discontinuity in transmission line: From viewpoint of imbalance factor and modal characteristic impedance

Abstract: For treating mode conversion caused by discontinuity in multi-conductor transmission line with circuit analysis, we have proposed a modal equivalent-circuit model with mode-conversion sources. The approach takes an advantage in less calculation sources and countermeasure consideration compared with full-wave simulation. A mode-decomposition technique was applied with an imbalance factor, that is, the current division factor in our study, of the transmission line. In the modal circuit analysis we proposed, mode conversion is expressed by the controlled sources of which magnitude is proportional to the difference between the current division factors of the adjacent transmission lines. In this paper, we focused on the modal transfer power and derived the mathematical expressions of the mode conversion using the modal characteristic impedance as well as the current division factor. For validating the derived equations, in addition, the comparison with full-wave simulation was carried out and a good agreement was confirmed.

Application of 3D stacking technology to SOI radiation image sensor

Abstract: Next generation pixelated radiation image detector requires intelligent data processing within each pixel Since the number of transistors implemented in the pixel area is limited, 3D stacking is indispensable technology in this kind of detector We have fabricated a stacked SOI radiation image sensor by using μ-bump technology of 5 μm pitch DC characteristics of transistors located in lower and upper tiers are successfully measured

Radio-frequency interference mitigation strategies for high-speed connectors

Abstract: Radio-frequency interference (RFI) issue becomes more and more significant in recent high-speed and small-form-factor electronic systems. Especially when their RF antennas cannot put away from digital input/output (I/O) interfaces, the coupling noise could highly degrade the antenna and system performance. In this problem, the amount of differential-mode noise is usually much larger than the common-mode one. For reducing the differential-mode noise, two useful mitigation strategies are suggested. These strategies are also workable for reducing the common-mode noise. For demonstration, a specific scenario of Wi-Fi dongle and its interface is defined and studied. Good mitigation results are indeed obtained for both common-and differential-mode cases by these strategies.

DFT for supply current testing to detect open defects at interconnects in 3D ICs

Abstract: In this paper, a Design-for-Testability method is proposed to detect an open defect occurring at an interconnect between dies in a 3D IC The open defect is detected by means of a supply current flowing whenever a time-varying voltage signal is provided to the targeted interconnect as a test input stimulus Feasibility of the test method is examined by targeted experiments and circuit simulations It is shown that an open defect in a testable designed IC is capable of being detected by measuring the supply current of the IC

Development of SiC power module for high-speed switching operation

Abstract: In this work, SiC power module with sandwich structure is fabricated for high-speed switching operation at high temperature. A module structure of SiC power devices are sandwiched between two silicon nitride-active metal brazed copper circuit boards. To make a precise position and height control of the chip bonding, the top side (gate/source or anode pad side) of SiC power devices are flip-chip bonded to circuit electrodes using sub-micron Au particle with low temperature (250°C) and pressure-less sintering. The accuracy of the bonding position of chips was less than 10 μm and the accuracy of the height after bonding chips was less than 15 μm. The flip-chip bonding of SiC-JFET is successfully realized on the substrate without short or open failure electrically. Finally we joint the backside of the SiC-JFET (drain side) and the SiC-SBD (cathode side) to each circuit electrodes at once by means of reflow process with Au-12%Ge solder. Since the sandwitch module showed no fatigue afetr 500 times thermal cycle test between -40°C and 250°C and showed properly operation. The circuit operation of the module is confirmed by a double pulse-switching test.

Multi-GPU HIE-FDTD method for the solution of large scale electromagnetic problems

Abstract: In this paper, Multi-GPU hybrid implicit-explicit finite-difference time-domain (HIE-FDTD) method is proposed for the solution of large-scale electromagnetic problems. The HIE-FDTD method is one of the weakly conditionally stable algorithms which can use a larger time step size than that for the conventional FDTD method. Furthermore, the HIE-FDTD method is suitable for parallel computing because this method requires only the local matrix operations. First, the HIE-FDTD method is reviewed briefly. Second, the proposed method is described for the efficient electromagnetic field simulation. Finally, the efficiency of the proposed method is evaluated by some numerical results.

Anti-resonance peak shift due to variation of effective package inductance

Abstract: Power integrity is a serious issue in the in the modern CMOS digital systems, because power supply noise excited in core circuits induces logic instability and electromagnetic radiation. Therefore, chip-package co-design is becoming important by taking into consideration the total impedance of power distribution network (PDN) seen from the chip. Especially, parallel resonance peaks in the PDN due to the chip-package interaction induces the unwanted power supply fluctuation, and results in the degradation of signal integrity and electromagnetic interference (EMI). In this paper, peak frequency shift in the total PDN impedance in three test chips with different on-die PDN properties was observed when the package inductance was changed.

Comparing fast convolution and model order reduction methods for S-parameter simulation

Abstract: This paper presents a comparison of the model-order reduction and fast convolution techniques for the macromodel simulation. Model-order reduction techniques using the vector fitting method have been extensively employed. In parallel, convolution techniques using scattering parameters have demonstrated special properties that can be exploited by acceleration techniques to achieve superior performance. The comparison is performed using simulations for various blackbox data.

Hardware accelerator for 3D method of moments based parasitic extraction

Abstract: A Field Programmable Gate Array (FPGA) based hardware accelerator for multi-conductor parasitic capacitance extraction, using Method of Moments (MoM), is presented in this paper Due to the prohibitive cost of solving a dense algebraic system formed by MoM, linear complexity fast solver algorithms have been developed in the past to expedite the matrix-vector product computation in a Krylov sub-space based iterative solver framework However, as the number of conductors in a system increases leading to a corresponding increase in the number of right-hand-side (RHS) vectors, the computational cost for multiple matrix-vector products present a time bottleneck, especially for ill-conditioned system matrices In this work, an FPGA based hardware implementation is proposed to parallelize the iterative matrix solution for multiple RHS vectors in a low-rank compression based fast solver scheme The method is applied to accelerate electrostatic parasitic capacitance extraction of multiple conductors in a Ball Grid Array (BGA) package Speed-ups up to 13× over equivalent software implementation on an Intel Core i5 processor for dense matrix-vector products and 12× for QR compressed matrix-vector products is achieved using a Virtex-6 XC6VLX240T FPGA on Xilinx's ML605 board

Efficient modeling and analysis of multilayered power distribution network by using conformal mesh and block-type leapfrog scheme

Abstract: This paper describes an efficient modeling technique based on a conformal mesh and its application to a fast transient analysis using a block-type leapfrog scheme for the simulations of multilayered power distribution networks (PDNs). Compared with conventional rectangular and triangular mesh generations, the conformal mesh approach can provide fewer meshes by using subcells. As a result, the number of the circuit elements constituting an equivalent circuit model becomes much fewer than those of the conventional models. In addition, the topology of the circuit is suitable for the bock latency insertion method (block-LIM), which is based on the explicit time marching procedure in a leapfrog manner. Example simulations of a multilayered PDN with nonorthogonal contours and fine structures show that the proposed conformal modeling combined with the block-LIM is as accurate as and much more efficient than the conventional modeling techniques with a SPICE-like circuit solver.

Modeling and characterization of carbon-based heterogeneous interconnects for 3-D ICs

Abstract: In this paper, one novel heterogeneous interconnect scheme, which combines the graphene-built horizontal interconnects and vertical through silicon carbon nanotube bundle vias (TS-CNTBV), is proposed and investigated theoretically The equivalent circuit models for them are presented and combined The anomalous skin effect (ASE) is treated appropriately for graphene-built interconnects The distributed parameters as well as transmission characteristics are obtained numerically This work provides some useful information about carbon-based interconnects where the advantages of carbon nanomaterials can be exploited for the development of 3-D ICs

Time-domain analysis of circuits with frequency-dependent elements using a SPICE-like solver

Abstract: In this paper, a new time-domain analysis method is presented for circuits with frequency-dependent elements This method mainly deals with lumped circuits generated by the full-wave partial element equivalent circuit (PEEC) technique or other similar techniques It is proven in this paper that a linear time-invariant (LTI) system with frequency-dependent elements can be treated as a sum of several sub-systems with frequency-independent elements By performing frequency spectrum analysis of the input signal, each sub-system's input signal can be determined The output signal for each sub-system can then be generated by a transient analysis using a SPICE-like solver Based on such principle, the proposed method achieves a good performance in computation efficiency, causality and concision Finally, an example is given for demonstrating the validity and effectiveness of the method

Three-dimensional packaging structure for 3D-NoC

Abstract: In this paper, we propose a novel three-dimensional (3D) packaging structure for a network-on-chip (NoC) based a 3D system-on-chip (SoC). Our SiP is implemented by vertically connecting two homogeneous SoCs through an organic interposer; that is, two homogeneous SoCs are bonded face-to-face above and below the organic interposer. NoCs have routing capability that can communicate with each other even if opposing nodes are connected to different node pins, which enables high-speed communication between SoCs using low voltage and current. As the power supply and external I/O pins are implemented via the organic interposer, we performed simulations to assess power integrity (PI) and signal integrity (SI) compared to a conventional package. To assess vertical communication performance as a 3D package, we simulated high-speed characteristics using the organic interposer and through silicon vias (TSVs), and confirmed the superior performance of the organic interposer.

Estimation of mode-conversion of differential copper cables using lumped circuit parameters

Abstract: Relationship between an S-parameter component corresponding to mode conversion and lumped parameters is investigated for high-speed differential copper cables using the theory of multi-conductor transmission lines. Experimentally observed frequency dependence of Scd21 is reproduced by analytical theories. Small fabrication tolerance is clarified.

Mathematics of 2r-port S-parameter Estimation by the r-port measurements

Abstract: An estimation method of the 2r-port S-parameters for reciprocal circuits is presented. In this method, several known loads are connected to r ports in turn and reflection and transmission characteristics among the remaining r ports are measured. Therefore, there is no need to connect a network analyzer to the ports that are connected to the known loads. S-parameters are obtained by solving several linear equations and quadratic equations only. In addition, applying this method to estimate the S-parameters of an circuit model of an enclosure mounting an IC chip, validness of this method is confirmed.

On-chip decouplig capacitor preplacement for power integrity enhancement

Abstract: With the rapid technology scaling, logic devices are more susceptible to power distribution network (PDN) power noise. To relieve power noise, traditionally the gate capacitance of transistor is used for on-chip decoupling capacitor (decap). In this paper, we investigate the power integrity characteristics of on-chip decap, such as power noise and current consumption, and propose the decap preplacement flow to relieve them. Compared to the non-preplacement approach, experimental results show the worst instantaneous voltage drop(IVD) can be reduced by about 7.16% and average supply current can be reduced by 3.05% by using preplacement scheme.

Thermal analysis of three-dimensional ICs, investigating the effect of through-silicon vias and fabrication parameters

Abstract: Three-dimensional (3D) integration technology is a promising technology for future due to multiple advantages over traditional 2D integrated circuits. However, dividing an original large die into smaller ones and stacking them decreases thermal conductivity of the chip and therefore an increase in temperature is expected. Through-silicon vias (TSVs) which implement vertical interconnections for the stacked dies in 3D chips can help transferring heat to the heat sink of the chip. Some recent works introduce techniques for reducing the TSV count which may cause worsening heat conduction, hence increase the peak temperature of the chip. In this paper the effect of the TSV count as well as four other fabrication parameters on the maximum 3D chip temperature is investigated. It is observed that reducing TSV count has a negative side effect on maximum temperature in all studied cases and increasing number of layers of the 3D stack has the most significant negative effect on maximum temperature. For example, increasing number of layers from two to four increases maximum temperature by 37.5% at a constant TSV pitch of 80 μm. While increasing TSV count four times by doubling TSV pitch from 40 μm to 80 μm increases maximum temperature by about 10% for six layers 3D stack.

Signal integrity evaluation of segmental transmission line under real-world application

Abstract: We have proposed a novel transmission line structure called “segmental transmission line (STL)” in order to ensure high signal integrity (SI) in PCB traces already and we have also shown its high SI improvement capability in eye-diagrams. In this paper, we evaluate the STL from the real-world application view point for the first time, which is indispensable for next development step. As one of applications, we choose image-data transmission at 5 Gbps and 7.5 Gbps data-rate, and demonstrate that the STL can transmit much higher quality image-data than the conventional transmission line by not only simulations but by a 500 Mbps STL scale-up prototype. We also calculate bit error rates (BERs) and show that BERs in the conventional transmission line decrease to 1/14 and 1/25 at 5 Gbps and 7.5 Gbps, respectively in the STL.

Crosstalk-noise reduction in GHz domain using segmental transmission line

Abstract: So far, the only effective way to decrease crosstalk-noise has been to widen space or to put shield trace between traces in PCBs. On the other hand, crosstalk-noise increases as the frequency increases, so that novel approaches to reduce the crosstalk-noise are strongly required in the GHz domain. We have applied a new trace structure “Segmental Transmission Line (STL)” to the crosstalk-noise reduction already and have shown its fundamental effectiveness for the clock signal transmission. In this paper, we apply the STL to reduce crosstalk-noises caused by random data signal in GHz domain and demonstrate that the STL can reduce the crosstalk-noise to about half of it in the uniform-width trace.

Design and analysis of high-speed and low power Si interposer for highperformance 3D stacked systems

Abstract: For IO interconnection, longer wiring induces larger signal delay and the driving power consumes proportionally the length of wiring. Therefore, high speed and low power IO design is definitely important for how to shorten wiring or to reduce power even relative longer wiring. Si interposer composed multi-chip (2.5D) provides more wiring space, however length of wiring would be longer than 3D-designed chip wiring. Thus, low-power IO system design must be required even in denser configuration. This paper is discussed from fundamental approach for reducing power of IO system.

Hybrid simulation of ESD events by SPICE-like and finite-difference time-domain methods

Abstract: In this paper, we describe a hybrid circuit and electromagnetic simulation technique for electrostatic discharge (ESD) events First, we perform the transient simulation of an equivalent circuit of an ESD generator At the same time, a computational domain without the ESD generator is analyzed by means of the finite-difference time-domain (FDTD) method The results from the SPICE-like and FDTD simulations are exchanged for each other by using analogy between the circuit theory and electromagnetics The proposed method can reduce the computational cost significantly because we perform the FDTD simulation only for the reduced domain, which is much smaller than the whole domain The adequacy of the proposed method is verified by comparing simulation results with measurement results

Fast transient analysis of power/ground planes based on multi-rate locally implicit latency insertion method

Abstract: This paper describes a multi-rate locally implicit latency insertion method (LILIM) for the fast simulations of power distribution networks (PDNs) modeled by triangular meshes. The original LIM is the transient analysis method based on an explicit leapfrog scheme, and the LILIM is the numerical analysis method constructed by applying a locally implicit scheme to the original LIM. The proposed method improves the existing LILIM by exploiting multi-rate behavior of a circuit and using adaptive time step size for each subcircuit.

On simultaneous escape routing of length matching differential signalings

Abstract: In substrate or PCB design, the escape routing problem is considered an essential part and has been widely studied in literature. There are industrial tools and some studies that work on simultaneous escape routing and escape routing of differential pairs on dense circuit boards. However, to route differential pairs simultaneously considering length-matching is still an important and on-going research problem. In this work, inspired by prior state-of-the-arts, we have implemented an integrated approach that achieves simultaneous escape routing considering length matching of differential pairs, our method avoids time-consuming ILP solutions in finding length-matching differential signal paths. Experimental results show that our approach can efficiently and effectively obtain length-matching of differential pairs on simultaneous escape routing to reduce differential-pair skews, compared with B-escape router we reimplemented.

Modal S-parameters and the circuit representation of symmetric circuits

Abstract: This paper presents guidelines for circuit analysis using symmetry, which is an extension of Bartlett's bisection theorem. The theory of modal S-parameters and the circuit representation are constructed from a group-theoretic perspective. The principles are explained with a simple circuit as an example. As a result, a finite combination of smaller circuits can characterize an entire circuit. This allows for easier understanding of the behavior. An analysis of a three-phase filter is performed as an application example.

Probability density calculation of step pulse responses at a 3-D IC channel with supply voltage fluctuations

Abstract: Causal transient step responses at a silicon interposer channel and at a wire-bond channel are calculated from the channel transfer functions obtained in frequency domain Also, the probability densities of the step response with supply voltage fluctuations are analytically calculated

MOSFET parasitic capacitance effects to class-DE power amplifier

Abstract: This paper presents analytical expressions for the class-DE amplifier with nonlinear drain-to-source and gate-to-drain capacitances. Using the analytical expressions, it is seen that drain-to-source capacitance works as linear shunt capacitance when the input signal is a square waveform. The validity of our analysis is confirmed by PSpice simulations and the circuit experiment.

Electrical capability assessment for high wiring density organic interposer

Abstract: Silicon and glass interposers provide a solution to keep scaling of C4 dimensions and chip-to-chip interconnect density by supporting high bandwidth However there are still some challenges in the fabrication process and cost As another alternative solution, organic material would be a candidate In order to perform the feasibility study for allowable bandwidth with organic material, various electrical parametric analyses were performed assuming simple chip-to-chip bus connection in the region of less than 10 μm trace width The results are indicating that the bandwidth with assumed organic material is comparable or more to one with SiO2 material and the trace width to obtain the bandwidth peak is 1-2 μm