Showing papers by "Actel published in 2002"

Tileable field-programmable gate array architecture

Abstract: An apparatus includes an FPGA, which includes a first FPGA tile including a plurality of FGs, a first, second, and third set of routing conductors, and a plurality of IGs. The FGs are arranged in rows and columns with each FG being configured to receive tertiary and regular input signals, perform a logic operation, and generate regular output signals. The third set of routing conductors is coupled to the first set of output ports of the FGs and configured to receive signals, route signals within the FPGA tile, and provide input signals to the third set of input ports of the FGs. The IGs surround the FGs such that one IG is positioned at each end of each row and column. Each IG is coupled to the third set of routing conductors and configured to transfer signals from the third set of routing conductors to outside the first FPGA tile.

Routing structures for a tileable field-programmable gate array architecture

Abstract: A field-programmable gate array (FPGA), comprising: a first FPGA tile, the first FPGA tile comprising a plurality of functional groups (FGs), a regular routing structure, and a plurality of interface groups (IGs). The plurality of FGs are arranged in rows and columns with each of the FGs being configured to receive regular input signals, perform a logic operation, and generate regular output signals. The regular routing structure is coupled to the FGs and configured to receive the regular output signals, route signals within the first FPGA tile, and provide the regular input signals to the FGs. The plurality of IGs surround the plurality of FGs such that one IG is positioned at each end of each row and column. Each of the IGs is coupled to the regular routing structure and configured to transfer signals from the regular routing structure to outside of the first FPGA tile. The first FPGA tile also comprising a secondary routing structure independent of the regular routing structure, coupled to each of the IGs, configured to transfer signals from said first FPGA tile to at least one other FPGA tile. The disclosed apparatus also provides for a routing structure between IGs and RAM blocks. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understand that it will not be used to interpret or limit the scope or meaning of the claims.

SRAM bus architecture and interconnect to an FPGA

Abstract: An SRAM bus architecture includes pass-through interconnect conductors. Each of the pass-through interconnect conductors is connected to routing channels of the general interconnect architecture of the FPGA through an element which includes a pass transistor connected in parallel with a tri-state buffer. The pass transistors and tri-state buffers are controlled by configuration SRAM bits. Some of the pass-through interconnect conductors are connected by programmable elements to the address, data and control signal lines of the SRAM blocks, while other pass through the SRAM blocks with out being further connected to the SRAM bussing architecture.

Field programmable gate array freeway architecture

Abstract: The disclosed system relates to a freeway routing system and a fast-freeway routing system for a field programmable gate array. The field programmable gate array comprises a two by two array of field programmable gate array tiles. Each tile comprises: a plurality of functional groups arranged in rows and columns; a plurality of interface groups surrounding the plurality of functional groups such that one interface group is positioned at each end of each row and column, each of the interface groups comprising a set of freeway input and output ports; a freeway set of routing conductors configured to transfer signals to the freeway input ports and from the output ports of the interface groups in each of the field programmable gate array tiles. The freeway set of routing conductors comprises: a plurality of vertical conductors that form intersections with a plurality of horizontal conductors; and programmable bi-directional three state interconnect elements located at the intersections. The fast-freeway routing system comprises: a first group of fast-freeway routing conductors, a second group of fast-freeway routing conductors, a third group of fast-freeway routing conductors, and a fourth group of fast-freeway routing conductors.

Inter-tile buffer system for a field programmable gate array

Abstract: An inter-tile buffering system for a field programmable gate array (FPGA) comprising a plurality of FPGA tiles arranged in rows and columns. Each file comprises a plurality of functional and interface groups and a primary routing structure, which is coupled to the functional and interface groups and is configured to receive and route primary output signals within at least one FPGA tile, and provide primary input signals to the functional and interface groups. Each functional group is configured to receive input signals, perform logic operations, and generate output signals and is configured to transfer signals from the routing structure to outside of at least one FPGA file, and includes a plurality of input multiplexers configured to select signals received from outside at least one FPGA tile and provide signals to the routing structure inside at least one FPGA tile.

Encryption for a stream file in an fpga integrated circuit

Abstract: A method and apparatus for encrypting a data stream (310) used to program an FPGA device comprising determining if there is at least one gap in the data stream (320); determining whether encryption is enabled for the at least one gap in the data stream, and encrypting the data stream, if encryption is enabled for the at least one gap. A method and apparatus for de-encrypting an encrypted data stream used to program an FPGA device comprising determining if there is at least one gap in the data stream; determining whether encryption was encabled for the at least one gap in the data stream; and decrypting the data stream, if encryption was enabled for the at least one gap.

Metal-to-metal antifuse employing carbon-containing antifuse material

Abstract: A metal-to-metal antifuse (22) is disposed between two metal interconnect layers in an integrated circuit. An insulating layer (18) is disposed above a lower metal interconnect layer (16). The insulating layer includes a via formed therethrough containing a tungsten plug (20) in electrical contact with the lower metal interconnect layer. The tungsten plug forms a lower electrode of the antifuse. The upper surface of the tungsten plug is planarized with the upper surface of the insulating layer. In a first embodiment, an antifuse material layer (22) comprising amorphous carbon, amorphous carbon doped with hydrogen or fluorine, or amorphous silicon carbide is disposed above the upper surface of the tungsten plug. A layer of a barrier metal (24) disposed over the antifuse material layer forms an upper electrode of the antifuse. An oxide (28) or tungsten hard mask provides high etch selectivity and the possibility to etch barrier metals without affecting the dielectric constant value and mechanical properties of the antifuse material. In a second embodiment, a layer of barrier material is disposed between the top surface of the tungsten plug and the antifuse material layer. An adhesion-promoting layer may be used where amorphous carbon is used as the antifuse material layer.

Field programmable gate array architecture including a buffer module and a method of distributing buffer modules in a field programmable gate array

Abstract: The present system comprises a device and a method for increasing the performance and utilization in a field programmable gate array (FPGA). The device of the present system comprises an FPGA having logic clusters, wherein each logic cluster further comprises a buffer. The method of the present system comprises a method of determining which buffers situated in each logic cluster are located in the best position in the post-placement user netlist to decrease the capacitance in the user netlist.

User available body scan chain

Abstract: A method of accessing the testing means in a Field Programmable Gate Array (“FPGA”) comprised of a plurality of functional groups (“FGs”) comprising: inputting a function netlist defining a user circuit; compiling said function netlist; and generating a logic Built-In Self Test (“BIST”) netlist; wherein said BIST netlist replaces all user registers with scan registers with a scan chain routed as the physical silicon scan chains.

Programming methods for an amorphous carbon metal-to-metal antifuse

Abstract: In a first embodiment, programming pulses of about 0.25 mA to about 0.5 mA are applied to an amorphous carbon based antifuse in first and second directions for 10 us to form an antifuse link having a finite resistance of less than 2000 ohms. Soaking pulses of about 2 mA to about 5 mA are then applied to the amorphous carbon antifuse in first and second directions for 1 ms and then repeated up to four more times to form an antifuse link with a finite resistance of about 100 ohms to about 400 ohms. In a second embodiment, programming pulses of about 0.25 mA to about 0.5 mA are applied to an amorphous carbon based antifuse in first and second directions for 1 ms and then repeated four more times to form an antifuse link having a finite resistance of less than 2000 ohms. Soaking pulses of about 2 mA to about 5 mA are then applied to the amorphous carbon antifuse in first and second directions for 1 ms and then repeated up to four more times to form an antifuse link with a finite resistance of about 100 ohms to about 400 ohms.

Field-programmable gate array architecture

Abstract: A field-programmable gate array (FPGA) is disclosed. A two-by-two array of FPGA tiles is surrounded by a JTAG interface, a Configuration interface and a BIST interface. Each interface is located adjacent to an outer edge of the two-by-two array of FPGA tiles. A plurality of boundary scan register chains are located adjacent to an outer perimeter of the two-by-two array of FPGA tiles and the JTAG, Configuration and BIST interfaces. A plurality of RAM blocks are located adjacent to an outer perimeter of the plurality of boundary register scan chains. A plurality of input/output pad rings is located adjacent to an outer perimeter of the plurality of ram blocks.

Panel: Reconfigurable SoC- What will it look like

Abstract: The argument against ASIC SoCs is that they have always taken too long and cost too much to design. As new process technologies come on line, the issue of inflexible, unyielding designs fixed in silicon becomes a serious concern. Without the flexibility of reconfigurable logic, will standard cell ASICs disappear and go the way of gate arrays? Will ASIC manufacturers lose their edge in providing intellectual value and become mere purveyors of square die area? The argument in favor of FPGAs is that they have always provided great design flexibility because they were configurable. The argument against FPGAs is that compared to ASICs they have always been larger, slower and more expensive. Will FPGAs ever become efficient enough to replace ASICs in volume production applications? ASSPs can be designed with partial reconfigurability. Will they become the norm? Or, will new reconfigurable logic cores change the SoC game completely? The answers to these questions will clearly impact system designers throughout the world and shape the future of the electronics industry. A panel of key industry executives each coming from a different area of the market with unique views will debate these highly controversial topics.

Method and apparatus of memory clearing with monitoring memory cells

Abstract: A field-programmable gate array (FPGA) comprising an array of RAM memory cells comprising at least one row of RAM memory cells, each RAM cell of the at least one row of RAM memory cells coupled to a row driver line; a row decoder coupled to a first end of the row driver line of each at least one row of RAM memory cells; a monitoring memory cell coupled to at least one of the row driver line; and where each monitoring memory cell is also coupled to a memory writing line. A method for an FPGA having a plurality of RAM memory cells as the programming mechanism, the FPGA further having erase circuitry for clearing the RAM memory cells for reprogramming of the FPGA. The method comprises providing at least one monitoring memory cell coupled to the erase circuitry; initiating a memory clear phase on at least one monitoring memory cell; and making a determination as to whether the output signal from each at least one monitoring memory cell indicates a cleared monitoring memory cell. The disclosed method may further comprise an act of writing to the at least one monitoring memory cell and a query of determining whether all of the at least one monitoring cell was properly written to. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understand that it will not be used to interpret or limit the scope or meaning of the claims.

Carry chain for use between logic modules in a field programmable gate array

Abstract: A field programmable gate array comprising a plurality of logic modules each logic module having two clusters, said logic modules arranged in rows and columns. The logic module clusters having a plurality of receiver components, a plurality of transmitter components, at least one buffer module, and at least one sequential logic components. Each logic module also comprises at least one left combinatorial logic unit having a carry-in input and carry-out output and at least one right combinatorial logic unit having a carry-in input and carry-out output adjacent to said left combinatorial logic unit. The carry-out output of the left combinatorial unit is hardwired to the carry-in input of said right combinatorial logic unit providing dedicated carry-in/carry-out logic circuitry.

Freeway routing system for a gate array

Abstract: A freeway routing system for connecting input and output ports of interface groups of tiles in a field programmable gate array. The freeway system has a first set of routing conductors configured to transfer signals between the input ports of interface groups in a first tile of the field programmable gate array and the output ports of interface groups of other tiles in the field programmable gate array. The first set conductors include vertical conductors that form intersections with horizontal conductors and programmable interconnect elements located at the intersections of the vertical conductors and horizontal conductors in a diagonal orientation to connect each of the horizontal conductors to one of the vertical conductors.

Method and apparatus for a flexible chargepump scheme for field-programmable gate arrays

Abstract: A programmable gate array comprising: a plurality of logic modules, each logic module having at least one output coupled to an isolation transistor, each isolation transistor in each of the plurality of logic modules having a gate; and a charge pump having a pump-voltage output line coupled to the gates of each isolation transistor in each of the plurality of logic modules. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims, 37 CFR 1.72(b).

Apparatus for interfacing and testing a phase locked loop in a field programmable gate array

Abstract: An apparatus for interfacing a phase locked loop in a field programmable gate array. The apparatus comprising a phase locked loop cluster. The phase locked loop further comprising a plurality of RT modules, a plurality of RO modules, at least one TY module, a plurality of receiver modules and at least one buffer module. A phase locked loop selectively coupled to the RT modules, the RO modules, the TY modules, the receiver modules and at least one buffer module in the phase locked loop cluster.

Antifuse programmable resistor

Abstract: A user-programmable resistor module includes a resistive element connected in series with first and second antifuses between an input circuit node and an output circuit node. Third and fourth antifuses are connected in series between the input circuit node and the output circuit node. A first programming transistor is connected between the common connection of the resistive element and the first antifuse and a first programming voltage node. A second programming transistor is connected between the common connection of the first and second antifuses and a fixed voltage node such as ground. A third programming transistor is connected between the input circuit node and the first programming voltage node. A fourth programming transistor is connected between the common connection of the third and fourth antifuses and a fixed voltage node such as ground. If the user-programmable resistor module described herein is used alone, a termination programming transistor is connected between the output circuit node and a second programming voltage node.

Radiation Tolerant Antifuse FPGA

Abstract: The total dose performance of the antifuse FPGA for space applications is summarized. Optimization of the radiation tolerance in the fabless model is the main theme. Mechanisms to explain the variation in different products are discussed.