Showing papers by "STMicroelectronics published in 1988"

A physically based mobility model for numerical simulation of nonplanar devices

Abstract: A semiempirical model for carrier mobility in silicon inversion layers is presented. The model, strongly oriented to CAD (computer-aided design) applications, is suitable for two-dimensional numerical simulations of nonplanar devices. A local mobility function, set up in terms of a simple Mattiessen's rule, provides a careful description of MOSFET operation in a wide range of normal (or gate) electric fields, channel impurity concentrations of between 5*10/sup 14/ cm/sup -3/ and 10/sup 17/ cm/sup -3/ for the acceptor density of states and 6*10/sup 14/ cm/sup -3/ and 3*10/sup 17/ cm/sup -3/ for the donor density of states; and temperatures between 200 K and 460 K. Best-fit model parameters are extracted by comparing the calculated drain conductance with a very large set of experimental data points. >

Smart Power

Abstract: It is argued that thanks to the development of new power technologies, the separate paths taken by power semiconductors and small signal ICs are converging onto a single discipline: smart power. Integrating high power and high voltage devices plus control circuits on a single chip, smart power ICs bring substantial reduction in cost and enhanced reliability. Moreover, they render feasible solutions that would have been too costly when realized with conventional components. Several different technological approaches to smart power have been explored, but all such technologies share the same basic concept of merging different stcuctures on the same chip, taking advantage of the similarities in processing techniques. Smart power technologies can be classified in a number of ways, the first of which is the isolation technique used: dielectric, junction or self isolation. A further way to classify smart power processes regards the current flow in the power devices. Another fundamental distinction between smart power processes is the nature of the power elements. Two options are available: bipolar and DMOS. Smart power devices can also be divided into single-chip types and single package types.

Programmable summing functions for programmable logic devices

Abstract: A programmable logic device includes a programmable logic array and an output logic macrocell The output logic macrocell includes a user configurable summing function that has a first logic gate connected to receive a first plurality of product terms, a second logic gate connected to receive a second plurality of product terms and a third logic gate connected to receive the combination of the first plurality of product terms and a controls signal, a fourth logic gate connected to receive the combination of the second plurality of Product Terms and the control signal and a logic circuit connected to receive the output signals from the first, second, third and fourth logic gates and to provide a first logical combination when the control signal is at a first logic state and a second logical combination when the controls signal is at a second logic state

Process for manufacturing CMOS integrated devices with reduced gate lengths

Abstract: A process for manufacturing CMOS integrated devices with gate lengths of less than one micron and high supply voltage is described. In order to improve the resistance of CMOS devices to breakdown and punch-through phenomena without cost increases with respect to conventional CMOS processes and limiting as much as possible the introduction of resistances in series to the transistors, less doped source and drain regions being provided in only one of the two MOS transistors, e.g. in the N-channel transistor, to increase the breakdown voltage, an oppositely doped region, e.g. with P-type doping, being provided around the source and drain regions of this first transistor to protect this first transistor against punch-through, and doped wells being provided around the source and drain regions of the complementary transistor, which is e.g. a P-channel transistor; the doped wells being oppositely doped with respect to the source and drain regions but having a lower doping level than the region of the body of semiconductor material which accommodates the complementary transistor, in order to increase the breakdown voltage of the P-channel complementary transistor.

Integrated active low-pass filter of the first order

Abstract: An integrated, low-pass filter of the first order made using the switched capacitors technique utilizes advantageously a single switched capacitor and only two switches in contrast to the filters of the prior art which utilize two switched capacitors and four switches. The filter of the invention requires a smaller integration area and moreover exhibits a greater precision of its DC gain.

MOZART: a concurrent multilevel simulator

Abstract: MOZART, a concurrent fault simulator for large circuits described at the register-transfer, functional, gate, and switch levels, is described. The requirements of multilevel simulation have guided the definition of MOZART's syntax, value set, delay model, and algorithms. Performance is improved by reducing unnecessary activity. Two such techniques are levelized: two-pass simulation, which minimizes the number of events and evaluations, and list event scheduling, which allows optimized processing of simultaneous (fraternal) events for concurrent machines. Moreover, efficient handling of abnormally large or active fault machines can improve fault-simulator performance by several orders of magnitude. These and related issues are discussed; both analytical and experimental evidence is provided for the effectiveness of the solutions adopted in MOZART. A performance metric is introduced for fault simulation, based on comparison with the serial algorithm, and is more accurate than those used in the past. >

Comparator with extended common-mode input voltage range

Abstract: A comparator comprising two differential input stages (Q1 to Q4 and Q5 to Q8) which are connected in parallel and fed by a common constant circuit source (QB) whose current is passed either to both or only to the one or only to the other differential input stage, depending on whether the common-mode input voltage of the comparator is within, above or below a voltage range that is between the voltage values of the two poles (VC, VE) of a supply voltage source (B) of the comparator, and comprising a common current mirror circuit (Q9, Q10) which is associated with the outputs of both differential input stages and from which the comparator output signal is derived. At least one (Q1 to Q4) of the two differential input stages operates in common-base connection, with this differential input stage (Q1 and Q4) receiving its supply current from the common-mode input voltage source.

System for reserving a supply of goods or services

Abstract: To reserve a supply of a good or service, a chip type memory card is inserted into a terminal of a reserving device. This reserving device makes the reservation by sending indications about this reservation to a terminal located near the goods or services to be delivered. On the agreed date and at the agreed place, the renting party goes to this terminal and inserts his memory card therein. The terminal then tells him where and how he should get and use the service or good reserved by him. This system can be applied in particular when the good or service to be obtained by self-service concerns the renting of a vehicle.

An interactive menu-driven remote control unit for TV-receivers and VC-recorders

Abstract: The use of a menu-driven control for selection and adjustment in TV receivers and video recorders is proposed. The experimental interactive infrared remote control unit described uses a single-button arrangement. The design of the unit, the appearance of the menu, and the hierarchy of possible functions are shown. A simple illustration of how to use this control is given. >

Analog multiplex for sensing the magnitude and sense of the current through a H-bridge stage utilizing a single sensing resistance

Abstract: A circuit for sensing the magnitude and sense of a current flowing through the load of a H-bridge stage driving the load in a switching mode by means of a clocked, square-wave driving signal and the inverted signal thereof applied, re­spectively, to two pairs of analog switches arranged in a bridge configuration and functionally switching the load between a supply node and a virtual ground node is made by utilizing a single sensing resistance connected between the virtual ground node and the real ground node of the circuit, the signal across the resistance and the inverted signal thereof are fed to two inputs of an analog multiplex whose output signal is fed to the input of a comparator in order to obtain at the output of the latter a signal with an amplitude proportional to the intensity of the current and a polarity determined by the polarity of a reference voltage which is applied to another input of the comparator. The PWM control loop may then be completed by means of a flip-flop to the inputs of which the output signal of the comparator and a clock signal are applicable in order to generate at the output of the flip-flop the clocked driving signal.

Process of forming an isolation structure

Abstract: Two thin wedges of oxide extending along and from the boundaries of the field oxide layer without solution of continuity inside the substrate for a depth such as to separate dielectrically the region of silicon, present underneath the field oxide layer, having a doping level higher than the doping level of the bulk of the substrate and the regions of oppositely doped silicon in a MOS device allow obtaining simultaneously a high threshold voltage of the parasitic transistor, a high junction breakdown voltage and an excellent immunity to "Reach-through" between the depletion regions of uncorrelated junctions together with a reduced capacitance of the junctions and an improved geometry. Such wedges of oxide are obtained by means of deep anisotropic etch of silicon through a suitably exposed area, for example by means of an overetch of the nitride used for growing the thick oxide layer according to the known technique and by the subsequent filling of the deep etch with thermally grown silicon oxide.

A 1-Mbit CMOS EPROM with enhanced verification

Abstract: A high-speed 1-Mb EPROM (erasable programmable read-only memory) with an enhanced verify mode to insure adequate threshold shift after programming has been developed. The sense circuitry uses an offset current to shift the sense point to require higher threshold shift during verification. The access time is improved by a clocking scheme that balances the sensing circuitry between column accesses and by a chip architecture optimized for speed. The chip features an access time of 70 ns and an active current of 20 mA. A typical programming time of 50 mu s has been measured. The device is processed in a 1- mu m L/sub eff/ CMOS process with silicides. >

High-dynamics amplifier stage with distortion detection

Abstract: In an amplifier stage comprising a pair of input current sources, connected in series between a pair of reference potential lines, a pair of output transistors connected between the pair of reference potential lines and defining an intermediate output terminal of the amplifier, a driving circuit comprising active elements and interposed between the input current source and the output transistors, and at least one saturation control circuit comprising at least one control transistor connected with its base to the driving circuit and with its collector and emitter between the output of the amplifier stage and the intermediate point between the input current sources, to detect distortion due to clipping, at least one distribution detection transistor is provided, connected to the control transistor so as to detect the current flowing through the latter, which current is related to the imbalance of the input current sources and therefore to the distortion generated in the stage.

Binary logic level electrical detector namely to prevent the detection of secret codes contained in a memory card

Abstract: To prevent fraudulent action by ill-intentioned users, the detection of the secret codes, contained in a memory card with MOS integrated circuit and transmitted to an input/output unit, is prevented. This is done by interposing a read amplifier in the transmission chain, in the integrated circuit itself. This read amplifier essentially has two parallel-connected identical circuits, designed to take complementary logic states when they receive one and the same logic level to be detected. The result of this is that the electrical comsumption of the amplifier is the same regardless of the logic level transmitted. Thus, it becomes impossible to deduce the nature of the logic level transmitted. As an improvement, the outputs of the detector are provided with bistable circuits which are coupled to each other so as to be capable of taking transitory or spurious information detected into account.

Method to expand an analog signal and device to implement the method

Abstract: A method for enlarging part of an analog input signal, and a circuit to implement this method. The circuit includes an amplifier which receives the analog input signal, the gain of which is controlled by a programming signal which varies as a function of the leading edge of the analog input signal and of a maximum threshold of the output signal from the circuit. A subtractor receives a substraction signal which is a function of an upper threshold and a lower threshold of the output signal from the circuit, and a signal from the amplifier, and then provides the output signal from the circuit.

Method for the optical reading of bar codes

Abstract: Disclosed is an improvement in methods for reading bar codes, enabling the codes to be read even under difficult conditions of uneven printing, stained background, poor contrast, cut bars etc. Instead of merely detecting light absorption or reflection spikes when a detector is moved in front of the code, where the presence of a bar is indicated when a threshold is exceeded, the following method is used: a matrix image of black and white pixels is set up; the sum Tj of black pixels of each column is counted to draw up a curve Tj as a function of the abscissa j of columns; a threshold SDA is established for Tj, below which, in principle, the columns do not contain a portion of a bar code bar; blocks of columns going beyond the threshold SDA are demarcated, and all the other columns of the image are eliminated; then shape recognition is carried out on the remaining blocks to ascertain whether the block truly corresponds to a bar or not. The value SDA is established by a recurrent computation that brings into play the ratio between surfaces Sinf and Ssup, above and below the threshold SDA in the curve Tj= f(j).

Nonvolatile memory device with a high number of cycle programming endurance

Abstract: An electrically alterable, non volatile memory device capable of enduring a high number of cycles utilizes an array of "semidouble" cells, each formed by a pair of elementary EEPROM cells connected substantially in parallel and a single select transistor. A special program lines biasing circuit generating a bias voltage (V CG ) representative of a condition wherein one of the two elementary EEPROM structure is broken and sense amplifiers comprising a comparator circuit (0, 1, 2...7) comparing the current flowing through an addressed semidouble memory cell with the current flowing through a reference cell comprising a pair of virgin EEPROM type elementary cells ensure operability of each bit of the memory also when one of the two elementary cells supporting the bit fails. Differently from known memories, only the EEPROM structure is duplicated while column lines (BL00...BL07), select lines and ancillary circuitry don't require duplication.

Cmos power operational amplifier

Abstract: A CMOS power operational amplifier with large output voltage swing and high noise rejection is obtained by coupling a folded cascode type differential input stage and an output stage comprising an intermediate signal shifting amplifier and two common source output stages. Constant current generators inject into the drain of grounded gate MOS transistors pairs of said folded cascode type stage and of said intermediately signal shifting amplifier, respectively, a current which is pulled out of the source of the same grounded gate transistors by other constant current generators for increasing the effective transconductance of said grounded gate transistors pairs.

Electronic component support for memory card and product obtained thereby

Abstract: The disclosure relates to memory cards having an electronic component housed in a cavity. The electronic support has a first base made of silicon, with a small thickness (between 50 and 100 microns) and a thicker (between 200 and 300 microns) second base, which is deposited on the first base and is formed by a material which is harder than silicon, such as cobalt, vanadium, titanium or ceramic.

Integrated circuit with memory comprising a fraud-prevention device

Abstract: Disclosed is an integrated circuit comprising an electrically erasable programmable memory, the cells of which comprise a transistor with floating gate which is series connected with an access transistor, wherein, in order to prevent deterioration in the information stored in the transistors with floating gates, due to an excessive read voltage being applied to the cell, the circuit has, firstly, an additional cell constituted like the other cells and programmed in a state where its transistor with floating gate cannot be made conductive, the gate and the source of the transistor with floating gate of the additional cell being grounded, the drain and the gate of the access transistor receiving the memory reading voltage, and, secondly, a threshold comparator connected to the drain of the floating gate transistor to compare the voltage on this drain with the reading voltage and to give a signal in the event of any abnormal drop in the voltage at the drain. The invention can be applied to integrated circuits with memory.

Method for the testing of electrically programmable memory cells, and corresponding integrated circuit

Abstract: A method for testing electrically programmable memories is disclosed. To enable the measurement of the current of programmed cells and blank cells (and not only to check whether the cells are programmed or not), and to enable this measurement even after the memory has been encapsulated in a package, it is proposed herein to connect, in testing mode, the bit line of a cell to be tested with the programming terminals to which there is applied, in programming mode, the programming high voltage Vpp. A low voltage Vte is applied to this terminal in testing mode, and the current flowing between this terminal and the voltage source is measured. This current is the current of the tested cell.

Integrated circuit protected against electrostatic discharges, with variable protection threshold

Abstract: To protect integrated circuits as efficiently as possible against electrostatic discharges, by putting a diode in avalanche mode without untimely triggering of this avalance mode by overvoltages of non-electrostatic origin, the following solution is proposed: through an insulated gate surrounding the cathode of the diode, the threshold for transition into avalanche mode of the diode is modified according to the slope of the overvoltages appearing at the terminal to be protected. The gate is connected to the terminal by an integrating circuit in such a way that the overvoltages are applied to the gate with a certain delay, inducing a potential difference between the cathode and the gate which is all the greater as the front of the overvoltage is steep. The avalanche triggering threshold is higher in the latter case than in the former one, and it is thus distinguish between overvoltages of diverse origins.

Automatic traffic condition control system

Abstract: Vehicle traffic is controlled by equipping each vehicle (2) with a memory-card or chip-card reader (3) connected to receiving means for receiving a signal emitted by a traffic control post (5) or station. The use of such cards permits generalised usage by avoiding the need to standardise the devices to be installed permanently on the vehicles (and which can therefore be of varied technology) and by limiting the standardisation only to limited elements: the chip cards (4).

Device to detect the depassivation of an integrated circuit

Abstract: The depassivation of an integrated circuit is detected by using the fact that the passivation coat which covers this circuit participates in the coupling capacitances that exist between parallel metallized lines made on its surface. The variation in one of these capacitances, resulting from depassivation, leads to a modification of the dielectrical induction of a voltage step, emitted on one line, in another line. The resulting variation in the induced voltage is used to produce a logic signal that reveals this depassivation. This logic signal can be used to neutralize the functioning of the integrating circuit to be protected.

System for executing, scheduling, and selectively linking time dependent processes based upon scheduling time thereof

Abstract: A microcomputer has a processor arranged to share its time between a plurality of concurrent processes. Each process may have means (69) for indicating a time when the process may be executed. The processes may form a linked list of processes (T, U. V) awaiting scheduling for execution. A location (90) is provided for indicating the beginning of a timer list of processes awaiting execution and means (68) is provided for indicating the end of a timer list. The microcomputer may provide more than one timer list of processes of different priority. Each process may include a number of alternative components one or more of which is time dependent.

A 30 A 30 V DMOS motor controller and driver

Abstract: A power DMOS half bridge (R/sub on/=40 m Omega , 30-V operating voltage, 30 A peak current) for windshield-wiper motors is presented. Double speed (DC and 20 kHz PWM output), motor braking, full protection and fault detection functions, and timing sequence (up to 200 ms) are performed by an integrated circuit that integrates the pull-up power transistor as well as the signal circuits on a technology process that allows the integration of bipolar, CMOS, and power DMOS transistors. The power pull-down transistor is a discrete device mounted in the same power package (Multi-watt 11) on an isolated tab. >

Integrated high-voltage bipolar power transistor and low voltage MOS power transistor structure in the emitter switching configuration and relative manufacturing process

Abstract: A description is given of two versions of an integrated structure in the emitter switching configuration comprising a high-voltage bipolar power transistor and a low-voltage MOS power transistor. In the vertical MOS version, the emitter region of the bipolar transistor is completely buried, partly in a first N- epitaxial layer and partly in a second N- epitaxial layer; the MOS is located above the emitter region. The bipolar is thus a completely buried active structure. In the horizontal MOS version, in a N- epitaxial layer there are two P+ regions, the first, which constitutes the base of the bipolar transistor, receives the N+ emitter region of the same transistor; the second receives two N+ regions which constitute the MOS source and drain regions, respectively; the front of the chip is provided with metal plating to ensure the connection between the MOS drain and the bipolar emitter contacts.

Digital push-pull driver circuit

Abstract: A digital push-pull driver circuit having two output transistors alternately controlled to conduct by means of a data control circuit, at the common junction of which output transistors a load to be driven is connected. Between the gate electrode of each of the two output transistors and the data control circuit, one edge-steepness-reducing enable-dependent delay circuit is connected in each case. In this arrangement, the output of each delay circuit is connected to an enable input of the other delay circuit in each case. The delay times of the two delay sections are at least as long as the length in time of the pulse edges with reduced steepness.

Power on reset circuit for a MOS technology integrated circuit

Abstract: A powering circuit to start up a MOS technology integrated circuit consists of first means made up of an oscillator and a voltage-increasing device to generate, from a supply voltage, a voltage greater than said supply voltage, and second means to measure the difference between the supply voltage and the generated voltage and to generate a powering signal when the difference reaches a given threshold.

Device for structural testing of an integrated circuit

Abstract: Between a bit line decoder and the memory of an integrated circuit, there is interposed a gate circuit which is cascade-connected with a logic block of the integrated circuit. This arrangement makes possible the structural testing of the integrated circuit. Structural testing means to read and check the response given on the outputs of the logic blocks for a given state imposed on its inputs. This arrangement results in a reduction of the space required on the integrated circuit for testing, when compared with other solutions, which require specific connection circuits. This arrangement is particularly adapted to integrated circuits with a memory and with decoders that provide access to the memory. The arrangement will find particular application in the testing of memory cards where EPROM or EEPROM circuits are used.