Showing papers in "IEICE Transactions on Electronics in 1996"

Driving Source-Line Cell Architecture for Sub-1-V High-Speed Low-Power Applications

Abstract: A novel SRAM cell architecture for sub-1-V high-speed operation is proposed that uses neither low-V/sub th/ MOSFETs nor modified cell layout patterns A source-line, connected to the source terminals of the driver MOSFETs is controlled so that it is negative and floating in the read and write cycles, respectively This improved the bit-line access time by 1/4-1/2 at supply voltages of 05-10 V Limiting the bit-line swing reduces by 1/10 the writing power needed to charge them and allows faster write-recovery, as well The achievability of low-power 100-MHz operation over a wide range of supply voltages is demonstrated

A 250-622 MHz Deskew and Jitter-Suppressed Clock Buffer Using Two-Loop Architecture

Abstract: A 250-622 MHz clock buffer has been developed, using a two-loop architecture: a delay-locked loop (DLL) for deskew, and a frequency-locked loop (FLL) for reference frequency supply to the DLL. The DLL incorporates a current-mode phase detector which utilizes a flip-flop metastability to detect a phase difference in the order of 20 ps. A measured jitter is suppressed to less than 40 ps RMS over the operating frequency range. A DLL acquisition time of 150 ns typical is simulated at 400 MHz. A 0.4-/spl mu/m CMOS technology is used to fabricate the chip.

A 2.5-Gb/s 15-mW Clock Recovery Circuit

Abstract: This paper describes the design of a 25-Gb/s 15-mW clock recovery circuit based on the quadricorrelator architecture Employing both phase and frequency detection, the circuit combines high-speed operations such as differentiation, full-wave rectification, and mixing in one stage to lower the power dissipation In addition, a two-stage voltage-controlled oscillator is utilized that incorporates both phase shift elements to provide a wide tuning range and isolation techniques to suppress the feedthrough due to input data transitions Fabricated in a 20-GHz 1-/spl mu/m BiCMOS technology, the circuit exhibits an rms jitter of 95 ps and a capture range of 300 MHz

Capacitance Coupling Immune, Transient Sensitive Accelerator for Resistive Interconnect Signals of Subquarter Micron ULSI

Abstract: This paper presents a new circuit scheme called a transient sensitive accelerator (TSA) circuit for highly resistive interconnects. The TSA can reduce both delay time and crosstalk voltage. Using the TSA with an interconnect length of 30 mm reduces delay time and crosstalk voltage by 29% and 20%, respectively. A further advantage is that the TSA operates in self-time and thus can be applied to bidirectional signal communication.

Proposal of Fiber-Optic Radio Highway Networks Using CDMA Method

Abstract: This paper proposes an application of code division multiple access (CDMA) for fiber-optic radio highway network which is universally applicable for various type of personal radio services and radio air interfaces. The proposed system can asynchronously open the radio-free space among any microcells. The outage probability is theoretically analyzed and compared with conventional subcarrier multiplexing (SCM) method. It is clarified that CDMA method improves the number of the active RBSs due to its reduction effect of the optical signal beat noise.

A Current Direction Sense Technique for Multiport SRAM's

Abstract: This paper describes two techniques for low-power single-end multiport SRAMs: a current direction sense circuit and a write bit-line swing control circuit. The sense circuit's input node is clamped at an intermediate voltage level, and the circuit transforms current direction into a logic value. It operates four times faster than a CMOS inverter, when driver sizes are equal, When it is applied to a single-end multiport SRAM, access is accelerated 3.2 times faster than that with a CMOS inverter with no increase in power consumption. The write bit-line swing control circuit reduces the bit-line precharge level within the limit of correct operation by using a memory cell replica. The control circuit reduces power consumption for bit-line driving and pseudoread cell current by 40%.

SOI-DRAM Circuit Technologies for Low Power High Speed Multigiga Scale Memories

Abstract: This paper describes a silicon on insulator (SOI) DRAM which has a body bias controlling technique for high-speed circuit operation and a new type of redundancy for low standby power operation, aimed at high yield The body bias controlling technique contributes to super-body synchronous sensing and body-bias controlled logic The super-body synchronous sensing achieves 30 ns faster sensing than body synchronous sensing and the body-bias controlled logic realizes 80 ns faster peripheral logic operation compared with a conventional logic scheme, at 15 V in a 4 Gb-level SOI DRAM The body-bias controlled logic also realizes a body-bias change current reduction of 1/20, compared with a bulk well-structure A new type of redundancy that overcomes the standby current failure resulting from a wordline-bitline short is also discussed in respect of yield and area penalty