Showing papers in "Integration in 1984"

TL;DR: Attention is paid to fabrication tolerances, wire capacitance, wire resistance, coupling capacitances and capacitance associated with contacts and the aspect ratio of (non-rectangular) transistors.

TL;DR: AT2-optimal integer division circuits for n-bit integers for all computation times T in the range [ Ω(( log n) 2 ), O (√n) ].

TL;DR: The design of decorders in which only a limited number of cells of RAM are written to or read from during test mode is proposed, in order to keep the extra hardware for enhancing testability to as small as possible while causing a minimal or no degradation at all in the speed performance of RAM.

TL;DR: A systolic system is disclosed, which achieves the optimal VLSI-complexity AT 2 = O( n 4 ) time, which is relevant in image processing.

TL;DR: Utilization of the logic programming language Prolog in solving CAD/CAM/CAT problems is discussed and it is demonstrated through examples that solutions are obtained through proper problem definition rather than by algorithmic procedures.

TL;DR: Experiences have shown that PLMAP is more efficient in MOS circuit analysis than spice, and uses a relaxation method to analyze the piecewise linear circuit at one time point after another.

TL;DR: The problem of permuting the pins of modules in order to maximize the number of connections which can be achieved in the polysilicon level is shown to be equivalent to that of removing fewest edges in a certain graph to break all cycles and the problem is proved to be NP-complete.

TL;DR: The scope of this work is to present a fast near optimum VLSI architecture for solving an N -point FFT which exhibits T = ϑ (log log N ) and AT 2 = ϓ ( N 2 log 2 N log log N ).

TL;DR: The parallel shift sort is a hardware adaption of sorting by insertion that uses an array of identical cells of low complexity, it is well suited for VLSI implementation.

TL;DR: A Nordic Multi-Project-Chip organization with 26 design groups and 22 follow-up groups from five Nordic countries is described, aiming towards submicron technology MPC, which might be the only possible way for smaller companies and universities to have circuits made.

TL;DR: Two programming notations are briefly introduced, one based on applicative state transition systems, and the other based on the notion of computational wavefront, which employ a data-flow principle to facilitate the description of parallel data movements and executions in VLSI arrays.

TL;DR: The performance of the recursive design technique is described comparing it to a typical systolic array, and how data word size and convolution size may be expanded by movement up the architectural hierarchy is demonstrated.

TL;DR: A new hierarchical interchange format is presented which provides the framework for communication between CAD tools within a VLSI design environment and supports a true hierarchical multi-level design representation.

TL;DR: Two techniques for the minimization of the area of a Programmable Logic Array (PLA) are described and an upper bound and a lower bound for the number of rows in the segmented PLA are derived.

TL;DR: Device modeling based on the injection model is used in conjunction with the Spice 2 program to generate a two-dimensional description of an IIL gate without geometric constraints, and this technique represents an improved method of device structure optimization within a reasonable computation time.