Showing papers in "Journal of Circuits, Systems, and Computers in 1997"
TL;DR: By performing a detailed analysis of switching-mode power supplies based on swithed-capacitor circuits, their fundamental steady-state characteristics are found.
Abstract: By performing a detailed analysis of switching-mode power supplies based on swithed-capacitor circuits, their fundamental steady-state characteristics are found. A few basic step-down and step-up c...
61 citations
TL;DR: In this papar, a new data structure, interval tree (IT), is introduced for an interval graph that has many advantages compared to the data structures which are commonly used to solve the problems on interval graphs.
Abstract: In this papar, a new data structure, interval tree (IT), is introduced for an interval graph. Some important properties of IT are studies from the algorithmic point of view. It has many advantages compared to the data structures which are commonly used to solve the problems on interval graphs. Using the properties of IT, the following problems are solved on interval graphs: (i) shortest distances between any two vertices, and (ii) the diameter of the graph.
17 citations
TL;DR: The same pulsed field surprised eels and hamsters, suggesting seismic anomalous animal ehavious animal behavior (SAAB) as electro-physiological responses to the stimuli of electric pulses.
Abstract: The electromagnetic (EM) behavior of a geological fault is postulated to follow the mathematical model of a fault in seismology that illustrates seismic EM anomalies EMAs). Charge densities, +q and -q in C/m2 are generated at a fault zone by the change in seismic stress, α as dq/dt = -αdσ/dt - q/∊ρ, where σ,∊ and ρ are the charge generation constants measured in C/N, dielectric constant and reisitivity of bedrocks, respectively. A fault of length, 2a, plane area, A and the displacement or rupture time, τ gives pulsed charge densities, +q(t) and -q(t), or a dipole moment of P(t) = 2aAq(t) = αM0[∊ρ/(τ - ∊ρ) - exp(-t/∊ρ)] using the earthquake moment M0. Maxwell's equations for this dipole in a conductive earth give power spectra of EM waves at diferrent distances. Seismic electric signals (SES) including the DC VAN method can be explained as EM waves. Electrons with density n in the atmosphere are accelerated by the electric field and travel a distance l. resulting in the exictation and ionization of atmospheric molecules leading to earthquake lightning (EQL). They also polarize the ionosphere by disturbing the transmission of EM waves prior to an earthquake and artificial electronic noises. The same pulsed field surprised eels and hamsters, suggesting seismic anomalous animal ehavious animal behavior (SAAB) as electro-physiological responses to the stimuli of electric pulses.
17 citations
TL;DR: A new low-roundoff noise realization for narrow-band IIR digital filters with residue feedback and a block triangular system matrix is presented and shows that the proposed structure provides excellent performance in terms of output roundoff noise and coefficient sensitivity.
Abstract: A new low-roundoff noise realization for narrow-band IIR digital filters with residue feedback and a block triangular system matrix is presented. The block triangular form of the system matrix allows a reduction in the number of arithmetic operations required for the implementation and leads also to a realization which is suitable for high speed implementation. Numerical comparison between the proposed structure and three other low-noise structures shows that the proposed structure provides excellent performance in terms of output roundoff noise and coefficient sensitivity. The output roundoff noise is slightly higher than that of the optimal residue feedback realization proposed by Williamson9 but lower than the optimal realization without residue feedback proposed by Mullis, Roberts and Hwang.6,7 Further an efficient (in terms of speed) VLSI processor array implementation of the proposed IIR structure is also presented. The proposed implementation has been obtained by taking advantage of both the parallel feature of the residue feedback and the block triangular structure of the system matrix of the proposed realization. A hardware comparison between the proposed implementation and another implementation which is based on direct form shows that the proposed implementation provides a higher sampling rate for any narrow-band filter.
9 citations
TL;DR: The experiments showed that divided word line memory arrays with two or four memory cells in a block have better power-area product than those with more than four cells per block, and the area of a dividedword line memory array can be 15% to 27% larger than the area in a comparable nondivided word line array.
Abstract: Since on-chip caches account for a significant portion of the power budget of modern microprocessors, low power caches are needed in microprocessors destined for portable electronic applications. A significant portion of the power consumption of caches comes from accessing the cache memory array and most of the power consumption of the memory array comes from driving the bit line pairs (i.e., the column current). Various memory array architectures have been proposed to improve the word line delay and the column current. For example, in a divided word line memory array memory cells in each row are organized into blocks. Only the memory cells which are in the activated block have their bit line pairs driven, thus both improving the speed (by decreasing the word line delay) and lowering the power consumption (by decreasing the column current). In this paper we analyze the power-area tradeoffs of divided word line memories with different size blocks. We compare the area and power consumption of 16 Kbit and 64 Kbit memory arrays with 2, 4, 8, and 16 memory cells per block. Our experiments show that a divided word line memory array can lower the power consumption by 50% to 90% over a nondivided word line memory array. However, they consume more area; the area of a divided word line memory array can be 15% to 27% larger than the area of a comparable nondivided word line array. Our experiments also showed that divided word line memory arrays with two or four memory cells in a block have better power-area product than those with more than four cells per block.
9 citations
TL;DR: A method for accommodating lumped, linear or nonlinear boundary conditions into the Wave Digital simulation of either linear orNonlinear PDE systems is presented.
Abstract: The Wave Digital multidimensional discretization technique, recently proposed by A. Fettweis et al., is a potentially important new method for simulating systems of partial differential equations (PDEs), especially those that model processes appearing in nature. To date, no general method has appeared in the literature indicating how to accommodate boundary conditions in Wave Digital simulations. Since the incorporation of a consistent set of boundary conditions within a given PDE system is a necessary condition for that system even to possess a unique solution, it is clear that accounting for boundary conditions within numeric simulations is just as necessary. We present here a method for accommodating lumped, linear or nonlinear boundary conditions into the Wave Digital simulation of either linear or nonlinear PDE systems. Graphic results from the Wave Digital simulation of a simple acoustics problem are also given.
7 citations
TL;DR: Rigorous proof of the sufficiency of the "infinite visitation" property is given for both independent and correlated noise and it is shown that a mixing condition on the observations will assure convergence if the OBE algorithm is slightly modified.
Abstract: Given appropriate persistency of excitation, the ellipsoidal seta associated with optimal bounding ellipsoid (OBE) algorithms with an interpretable optimization (volume) criterion, converge to a point under the condition that the model disturbance process visit the error bounds infinitely often. The spectral properties of the disturbance are not primary in the convergence behavior of OBE algorithms, rendering these identifiers distinctly different from the structurally similar RLS. Rigorous proof of the sufficiency of the "infinite visitation" property is given for both independent and correlated noise. In the colored noise case, it is shown that a mixing condition on the observations will assure convergence if the OBE algorithm is slightly modified. Examples of simulations are used to illustrate the theoretical developments.
7 citations
TL;DR: An efficient simulation method is presented that generates thermal images and also gives tracking results of infra-red (IR) reticle seekers and is applicable to the study of the development of counter-countermeasures (CCMs).
Abstract: This paper presents an efficient simulation method that generates thermal images and also gives tracking results of infra-red (IR) reticle seekers. First, we make an IR model of the object with the internal heat source, and generate thermal images by the optical system of the reticle seeker and the atmospheric turbulence. Using the obtained thermal images, we can simulate IR reticle seekers in various scenarios including countermeasures (CM) such as flares. Simulation results show that we can generate more accurate images by using the proposed method, which is applicable to the study of the development of counter-countermeasures (CCMs).
4 citations
TL;DR: It is proved that for all vectors of branch voltages uℳ and currents iℹ in ℳ satisfying Kirchhoff's voltage and current laws in every loop and cutset of contained in ™ if and only if ℹ is a union of blocks of .
Abstract: Let be a directed network and ℳ its subnetwork. It is proved that for all vectors of branch voltages uℳ and currents iℳ in ℳ satisfying Kirchhoff's voltage and current laws in every loop and cutset of contained in ℳ if and only if ℳ is a union of blocks of . This yields a version of Tellegen's famous theorem for subnetworks.
4 citations
TL;DR: A new algorithm in which the delay of each critical signal path is within a specified upper bound imposed on it is presented, which resolves almost all path delay constraints while maintaining the maximum number of required I/O blocks per chip small compared with conventional algorithms.
Abstract: In this paper, we extend the circuit partitioning algorithm which we had proposed for multi-EPGA systems and present a new algorithm in which the delay of each critical signal path is within a specified upper bound imposed on it. The core of the presented algorithm is recursive bipartitioning of a circuit. The bipartitioning procedure consists of three stages: (0) detection of critical paths; (1) bipartitioning of a set of primary inputs and outputs; and (2) bipartitioning of a set of logic-blocks. In (0), the algorithm computes the lower bounds of delays for paths with path delay constraints and detects the critical paths based on the difference between the lower and upper bounds dynamically in every bipartitioning procedure. The delays of the critical paths are reduced with higher priority. In (1), the algorithm attempts to assign the primary inputs and outputs on each critical path to one chip so that the critical path does not cross between chips. Finally in (2), the algorithm not only decreases the number of crossings between chips but also assigns the logic-blocks on each critical path to one chip by exploiting a network flow technique. The algorithm has been implemented and applied to MCNC PARTITIONING 93 benchmark circuits. The experimental results demonstrate that it resolves almost all path delay constraints while maintaining the maximum number of required I/O blocks per chip small compared with conventional algorithms.
4 citations
TL;DR: The application of a radial basis function neural network (RBFN) for analog circuit fault isolation is presented and a method is suggested to select centers and widths of RBF units and modify the RBF network in the event of occurrence of a new fault.
Abstract: The application of a radial basis function neural network (RBFN) for analog circuit fault isolation is presented. In this method the RBFN replaces the fault dictionary of analog circuits. The proposed method for analog circuit fault isolation takes the advantage of extremely fast training of RBFN compared to earlier neural network methods. A method is suggested to select centers and widths of RBF units. This selection procedure accounts for the component tolerances. The effectiveness of the RBFN for the fault isolation problem is demonstrated with an illustrative example. RBFN performed well even when the input patterns are drawn directly from the test node voltages of the analog circuit under consideration. A method is suggested to modify the RBF network in the event of occurrence of a new fault. The suggested modifications do not affect the previous training.
TL;DR: Using a fixed point stability analysis it is shown that varying the inductor resistance it is possible to suppress or allow chaotic oscillations in Chua's circuit.
Abstract: This short paper discusses the effect of the internal resistance of the inductor in Chua's circuit which is often neglected by many even when actual implementation is intended. Using a fixed point stability analysis it is shown that varying the inductor resistance it is possible to suppress or allow chaotic oscillations. The results reported in this paper have clear consequences for the control of Chua's circuit.
TL;DR: The HK486, an Intel 80486 pin-compatible microprocessor successfully is designed and verified using the proposed verification methodology, and the confidence level of verifications is increased.
Abstract: As the complexity of microprocessors increases, functional verification becomes more difficult and emerges as the bottleneck of the design cycle. In this paper, we suggest a functional verification methodology, especially for compatible microprocessor designs. To guarantee perfect compatibility with previous microprocessors, we developed three C models in different abstraction levels, i.e. Polaris, MCV and StreC. An instruction behavioral level C model (Polaris) is verified using the slowed-down PC. In the implemetation of micro-architecture, a micro-operational level model (MCV) and RTL model (StreC) are co-simulated with consistency checking between these two models. The simulation speed of C models makes it possible to test the "real-world" application programs on the RTL design with a software board model (VPC). To increase the confidence level of verifications, Profiler reports the verification coverage of the test program, which is fed-back to the automatic test program generator (Pandora). The Restartability feature also helps to significantly reduce the total simulation time. Using the proposed verification methodology, we designed and verified the HK486, an Intel 80486 pin-compatible microprocessor successfully.
TL;DR: Applications of the transformation method and experimental results indicating the performance of the transformed current conveyor circuit compared with the original circuit are given.
Abstract: A transformation method which leads to the generation of high input impedance current conveyor based filters from finite input impedance circuits is given. Applications of the transformation method are included. PSpice simulations and experimental results indicating the performance of the transformed current conveyor circuit compared with the original circuit are also given.
TL;DR: Instead of linear and nonlinear, the circuit is divided into resistive and reactive parts, and most of the unknowns are expressed explicitly.
Abstract: Some considerations on initial partitioning of the circuit within harmonic balance analysis are presented Instead of linear and nonlinear, it is divided into resistive and reactive parts Following the procedure presented, frequency as a parameter appears no more than once inside each equation, and most of the unknowns are expressed explicitly The former is advantageous when examining an autonomous system, and the latter enables a simple numerical process The method proposed is illustrated by an example
TL;DR: This work presents a Collision-Free Reservation Protocol (CFRP) for WDM single-hop networks with a passive optical star coupler that enhances the overall network performance.
Abstract: WDM single-hop networks allow a pair of nodes to exchange data packets directly and require an efficient protocol that coordinates the process of data transmission. However, the network performance with such protocols can be deteriorated by collisions that occur on control channel, data channel, destination node and source node. We present a Collision-Free Reservation Protocol (CFRP) for WDM single-hop networks with a passive optical star coupler. To eliminate all causes of collision, the CFRP properly distributes the transmission schedule both in time (position of data channel on the time axis) and space (wavelength of data channel to be used). Compared with the previous reservation-based protocols, the proposed CFRP enhances the overall network performance. This improvement in terms of network throughput and delay is verified by simulation.
TL;DR: The algorithm is developed based on the wavelet transform, and the dominant local orientation which is derived from the coherence and the gradient of Gaussian, and does not require conventional preprocessing procedures such as smoothing, binarization, thining and restoration.
Abstract: In this paper, a fingerprint recognition algorithm is suggested. The algorithm is developed based on the wavelet transform, and the dominant local orientation which is derived from the coherence and the gradient of Gaussian. By using the wavelet transform, the algorithm does not require conventional preprocessing procedures such as smoothing, binarization, thining and restoration. Computer simulation results show that when the rate of Type II error — Incorrect recognition of two different fingerprints as identical fingerprints — is held at 0.0%, the rate of Type I error — Incorrect recognition of two identical fingerprints as different ones — turns out as 2.5% in real time.
TL;DR: The principal phenomena involved in the power consumption of CMOS circuits, a brief survey of power estimation techniques, and the effect of power-supply noise on circuit performance plus possible solutions to this problem are focused on.
Abstract: Power consumption is a primary concern for today's IC designers. However, determining an IC's power consumption is a difficult task, as consumption varies according to input stimulus conditions. This paper will focus on (1) the principal phenomena involved in the power consumption of CMOS circuits, (2) a brief survey of power estimation techniques, and (3) the effect of power-supply noise on circuit performance plus possible solutions to this problem.
TL;DR: It is shown that the proposed Walsh functions provide a straighforward and efficient algorithm for fast Discrete Walsh Transformation.
Abstract: A new set of Walsh functions is defined in terms of the split-matrix ordering. The intrinsic properties of the functions are analyzed. The relationship and the associated conversion rules between the newly defined functions and other typical Walsh functions are discussed. It is shown that the proposed Walsh functions provide a straighforward and efficient algorithm for fast Discrete Walsh Transformation.
TL;DR: Nonlinear semi-state equations for a bidirectional circuit representing a generic cochlea hair-cell are presented, which can be specialized to inner or outer hair-cells depending upon the choice of circuit parameter values.
Abstract: Cochlea hair-cells act as neural interfaces of sound signals and, therefore, circuit representations are important to signal processing systems based upon characteristics of the ear. Here nonlinear semi-state equations for a bidirectional circuit representing a generic cochlea hair-cell are presented. The circuit can be specialized to inner or outer hair-cells depending upon the choice of circuit parameter values. Also developed are a canonical semi-state description for the hair-cell potassium and sodium channels, and circuits suitable for a transistorized hardware implementation. Circuit simulations are run with numerical data to correlate with the Howard–Hudspeth experiments.
TL;DR: A new fractional-N programmable divider is proposed that is less than or equal to half of that of the conventional one and the width of phase error pulse is decreased by introducing the new division ratio (N + 1/2).
Abstract: Recently, the speedup of lock up time is required in the Phase Locked Loop (PLL) frequency synthesizer. The fractional-N method is one of the most important techniques among the speedup methods proposed hitherto. The fractional-N programmable divider can divide not only an integer step but also a fractional one. However, the phase detector always generates the phase error pulse in every period of reference frequency and the elimination of this phase error pulse seems to be difficult. In this paper, a new fractional-N programmable divider is proposed. In this divider, the width of phase error pulse is decreased by introducing the new division ratio (N + 1/2) besides N and (N + 1). Then, the width of maximum phase error pulse in the new fractional-N programmable divider is less than or equal to half of that of the conventional one.
TL;DR: A low-voltage MOS analog mixer using a cross-coupled pair as the core shows that the mixing characteristic is superior and not sensitive to device mismatches.
Abstract: A low-voltage MOS analog mixer using a cross-coupled pair as the core is described. The mixing operation is based on the square-law characteristic of MOS transistor operating in the saturation region. Theory, simulation and measurement show that the mixing characteristic is superior and not sensitive to device mismatches. The realized mixer achieved a DC nonlinearity of less than 0.7% experimentally within an input range of 0.6 Vp-p. The measured IM3 and IMFDR3 are 22.5 dBm and -46.7 dB respectively. It consumes 2 mW power from a single 3.3 V power supply. The active die area is 200 μm × 150 μm.
TL;DR: This paper is concerned with the exploitation of genetic algorithms and their application to the development of a new optimization technique for the high-level synthesis of digit-serial digital filter data-paths and the results obtained are compared to those of the existing techniques to confirm the validity of the technique.
Abstract: This paper is concerned with the exploitation of genetic algorithms and their application to the development of a new optimization technique for the high-level synthesis of digit-serial digital filter data-paths. In the resulting optimization technique, the cost associated with the final digital filter data-path is minimized subject to user-specified constraints on the number of physical arithmetic functional units employed. The proposed technique is capable of obtaining global area-optimal, time-optimal, or combined area-cum-time-optimal data-paths, where the optimality takes into account not only the cost associated with the required arithmetic functional units but also that associated with the required support cells (multiplexors and registers). This optimization is made computationally effective by encoding the digital filter data flow-graph into chromosomes which preserve the data-dependency relationships in the original digital filter signal flow-graph under the operations of crossover and mutation by the underlying genetic algorithm. The usefulness of the proposed technique is demonstrated by applying to the constrained optimization of a benchmark elliptic wave digital filter for full bit-serial, full bit-parallel, as well as general digit-serial high-level synthesis. The results thus obtained are compared to those of the existing techniques (whenever appropriate) to confirm the validity of the technique.
TL;DR: A method of low bit-rate facial image coding specifically designed for the use in video telephone to generate the replica of the sender's facial expression merely by deforming a master face image, which is sent once at the beginning of the telephone call.
Abstract: A method of low bit-rate facial image coding specifically designed for the use in video telephone is presented. The basic principle for this facial image coding is to exploit the capabilities of 2D image warping techniques to generate the replica of the sender's facial expression merely by deforming a master face image, which is sent once at the beginning of the telephone call. Several parameters that describe facial expressions are monitored at the transmitter at the video frame rate of 30 frames/s, and then transmitted to the receiver using the in-band data channel. Since transmission of actual image data happens once or when another image is required, the bit-rate is much lower that that required by ordinary video image transmission. A fast bilinear mapping method for warped images, a grid mesh set over the facial image, various warping algorithms to realize head movement and facial motions with respect to eyes and mouth are discussed. This paper also compares the presented low bit-rate facial image coding to its competing methods such as MPEG and the method using a 3D facial model.