Showing papers in "Journal of Semiconductor Technology and Science in 2008"
TL;DR: In this article, the authors evaluated non-stoichiometric polycrystalline oxides (Nb₂O 5, and ZrO x ) and subsequently the resistive switching of CU x O and heavily Cu-doped MoO x film for their compatibility with modern transistor-process cycles.
Abstract: Several oxides have recently been reported to have resistance-switching characteristics for nonvolatile memory (NVM) applications. Both binary and ternary oxides demonstrated great potential as resistive-switching memory elements. However, the switching mechanisms have not yet been clearly understood, and the uniformity and reproducibility of devices have not been sufficient for gigabit-NVM applications. The primary requirements for oxides in memory applications are scalability, fast switching speed, good memory retention, a reasonable resistive window, and constant working voltage. In this paper, we discuss several materials that are resistive-switching elements and also focus on their switching mechanisms. We evaluated non-stoichiometric polycrystalline oxides (Nb₂O 5 , and ZrO x ) and subsequently the resistive switching of CU x O and heavily Cu-doped MoO x film for their compatibility with modern transistor-process cycles. Single-crystalline Nb-doped SrTiO₃(NbSTO) was also investigated, and we found a Pt/single-crystal NbSTO Schottky junction had excellent memory characteristics. Epitaxial NbSTO film was grown on an Si substrate using conducting TiN as a buffer layer to introduce single-crystal NbSTO into the CMOS process and preserve its excellent electrical characteristics.
30 citations
TL;DR: In this article, the aspect ratio of a scaled multiple-gate FET (MuGFET) was investigated with the aid of 3D device simulations and it was shown that the triple-gate (TG) FET is superior to the conventional FinFET from the viewpoints of drivability and short-channel effects.
Abstract: This paper puts forward an advanced consideration on the design of scaled multiple-gate FET (MuGFET); the aspect ratio (R h/w ) of the fin height (h) to fin width (w) of MuGFET is considered with the aid of 3-D device simulations. Since any change in the aspect ratio must consider the trade-off between drivability and short-channel effects, it is shown that optimization of the aspect ratio is essential in designing MuGFET’s. It is clearly seen that the triple-gate (TG) FET is superior to the conventional FinFET from the viewpoints of drivability and short-channel effects as was to be expected. It can be concluded that the guideline of w ＜ L/3, where L is the channel length, is essential to suppress the short-channel effects of TG-FET.
30 citations
TL;DR: In this article, a brief overview of the history of polymer ferroelectric non-volatile memory and device architectures based on inorganic Ferroelectric materials is given. And various material and process issues for realization of poly(vinylidene fluoride) nonvolatile memories are discussed, including the control of crystal polymorphs, film thickness, crystallization and crystal orientation and unconventional patterning techniques.
Abstract: The article presents the recent research development in polymer ferroelectric non-volatile memory. A brief overview is given of the history of ferroelectric memory and device architectures based on inorganic ferroelectric materials. Particular emphasis is made on device elements such as metal/ferroelectric/metal type capacitor, metal-ferroelectric-insulator-semiconductor (MFIS) and ferroelectric field effect transistor (FeFET) with ferroelectric poly(vinylidene fluoride) (PVDF) and its copolymers with trifluoroethylene (TrFE). In addition, various material and process issues for realization of polymer ferroelectric non-volatile memory are discussed, including the control of crystal polymorphs, film thickness, crystallization and crystal orientation and the unconventional patterning techniques.
27 citations
TL;DR: In this paper, two approaches for tunnel barrier engineering are compared: the crested barrier and variable oxide thickness, and key results of TBE and its applications for NVM are also addressed.
Abstract: Tunnel oxide of non-volatile memory (NVM) devices would be very difficult to downscale if ten-year data retention were still needed. This requirement limits further improvement of device performance in terms of programming speed and operating voltages. Consequently, for low-power applications with Fowler-Nordheim programming such as NAND, program and erase voltages are essentially sustained at unacceptably high levels. A promising solution for tunnel oxide scaling is tunnel barrier engineering (TBE), which uses multiple dielectric stacks to enhance field-sensitivity. This allows for shorter writing/erasing times and/or lower operating voltages than single SiO₂ tunnel oxide without altering the ten-year data retention constraint. In this paper, two approaches for tunnel barrier engineering are compared: the crested barrier and variable oxide thickness. Key results of TBE and its applications for NVM are also addressed.
26 citations
TL;DR: X-Ray analysis has confirmed the formation of cadmium oxide (CdO) with slight increase in grain size, shift towards lower scattering angle due to relaxation in the tensile strain for deposition films, and structure change from cubic and hexagonal to the hexagonal.
Abstract: In this work CdS films were prepared by using chemical bath deposition, which is simple and inexpensive technique suitable for large deposition area. Annealing in air at different temperatures (300, 350, 400, 450 and 500 ℃) at constant time of 30 min, also for different times (15, 30, 45, 60 and 90 min) at constant temperature (300 ℃) is achieved. X-Ray analysis has confirmed the formation of cadmium oxide (CdO) with slight increase in grain size, shift towards lower scattering angle due to relaxation in the tensile strain for deposition films, and structure change from cubic and hexagonal to the hexagonal. From electrical properties, significant increase in electrical conductivity appeared in samples annealed at 300 ℃ for 60 min, and at 350 ℃ for 30 min.
26 citations
TL;DR: The model is useful in determining the ion implantation fabrication parameters from the optimization of the active implanted channel thickness for different ion doses resulting in the desired pinch off voltage needed for high drain current and high breakdown voltage.
Abstract: In this paper, we report an analytical mo- deling and 2-D Synopsys Sentaurus TCAD simulation of ion implanted silicon carbide MESFETs. The model has been developed to obtain the threshold voltage, drain-source current, intrinsic parameters such as, gate capacitance, drain-source resistance and transconductance considering different fabrication parameters such as ion dose, ion energy, ion range and annealing effect parameters. The model is useful in determining the ion implantation fabrication parameters from the optimization of the active implanted channel thickness for different ion doses resulting in the desired pinch off voltage needed for high drain current and high breakdown voltage. The drain current of approximately 10 A obtained from the analytical model agrees well with that of the Synopsys Sentaurus TCAD simulation and the breakdown voltage approximately 85 V obtained from the TCAD simulation agrees well with published experimental results. The gate-to-source capacitance and gate-to- drain capacitance, drain-source resistance and trans- conductance were studied to understand the device frequency response. Cut off and maximum frequencies of approximately 10 GHz and 29 GHz respectively were obtained from Sentaurus TCAD and verified by the Smith's chart.
21 citations
TL;DR: The structure of 2-bit/cell flash memory device was characterized for sub-50 nm non-volatile memory (NVM) technology and it was shown that peak of trapped charge density was observed near ~10 nm below the source/drain junction.
Abstract: The structure of 2-bit/cell flash memory device was characterized for sub-50 nm non-volatile memory (NVM) technology. The memory cell has spacer-type storage nodes on both sidewalls in a recessed channel region, and is erased (or programmed) by using band-to-band tunneling hot-hole injection (or channel hot-electron injection). It was shown that counter channel doping near the bottom of the recessed channel is very important and can improve the V th margin for 2-bit/cell operation by ~2.5 times. By controlling doping profiles of the channel doping and the counter channel doping in the recessed channel region, we could obtain the V th margin more than ~1.5V. For a bit-programmed cell, reasonable bit-erasing characteristics were shown with the bias and stress pulse time condition for 2-bit/cell operation. The length effect of the spacer-type storage node is also characterized. Device which has the charge storage length of 40 nm shown better △V th and V th margin for 2-bit/cell than those of the device with the length of 84 nm at a fixed recess depth of 100 nm. It was shown that peak of trapped charge density was observed near ~10 nm below the source/drain junction.
20 citations
TL;DR: It is verified experimentally that the use of the MEMS inkjet head allows a stable and sustainable micro- dripping mode of droplet ejection and electric field intensity according to the head structure.
Abstract: This paper presents design and fabrication of optimized geometry structure of electrostatic inkjet head. In order to verify effect of geometry shape, we simulate electric field intensity according to the head structure. The electric field strength increases linearly with increasing height of the micro nozzle. As the nozzle diameter decreases, the electric field along the periphery of the meniscus can be more concentrated. We design and fabricate the electrostatic inkjet heads, hole type and pole type, with optimized structure. It was fabricated using thick-thermal oxidation and silicon micromachining technique such as the deep reactive ion etching (DRIE) and chemical wet etching process. It is verified experimentally that the use of the MEMS inkjet head allows a stable and sustainable micro- dripping mode of droplet ejection. A stable micro dripping mode of ejection is observed under the voltages 2.5 kV and droplet diameter is 10 μm.
18 citations
TL;DR: The results show that for this ratio of effective channel length to natural/ characteristic length to be greater than 2, steeper source/drain doping gradients along with wider source/Drain rolloff widths will be required for both devices.
Abstract: In the present work a methodology to minimize short channel effects (SCEs) by modulating the effective channel length is proposed to design 25 ㎚ single and double gate-source/drain underlap MOSFETs. The analysis is based on the evaluation of the ratio of effective channel length to natural/ characteristic length. Our results show that for this ratio to be greater than 2, steeper source/drain doping gradients along with wider source/drain rolloff widths will be required for both devices. In order to enhance short channel immunity, the ratio of source/drain roll-off width to lateral straggle should be greater than 2 for a wide range of source/drain doping gradients.
13 citations
TL;DR: In this article, the authors investigated the resistive switching properties of thin TiO₂ films on Pt/Ti/SiO/Si/Si substrates that were embedded with a Co ultra thin layer.
Abstract: We systematically investigated the resistive switching properties of thin TiO₂ films on Pt/Ti/SiO₂/Si substrates that were embedded with a Co ultra thin layer. An in-situ sputtering technique was used to grow both films without breaking the chamber vacuum. A stable bipolar switching in the current-voltage curve was clearly observed in TiO₂ films with an embedded Co ultra thin layer, addressing the high and low resistive state under a bias voltage sweep. We propose that the underlying origin involved in the bipolar switching may be attributed to the interface redox reaction between the Co and TiO₂ layers. The improved reproducible switching properties of our novel structures under forward and reverse bias stresses demonstrated the possibility of future non-volatile memory elements in a simple capacitive-like structure.
12 citations
TL;DR: In this article, a post-linearization technique for the differrential CMOS LNA is presented, which uses an additional cross-coupled common-source FET pair to cancel out the third-order intermodulation (IM₃) current of the main differential amplifier.
Abstract: A post-linearization technique for the differrential CMOS LNA is presented. The proposed method uses an additional cross-coupled common-source FET pair to cancel out the third-order intermodulation (IM₃) current of the main differential amplifier. This technique is applied to enhance the linearity of CMOS LNA using 0.18-㎛ technology. The LNA achieved +10.2 ㏈m IIP3 with 13.7 ㏈ gain and 1.68 ㏈ NF at 2 ㎓ consuming 11.8 ㎃ from a 1.8-V supply. It shows IIP3 improvement by 6.6 ㏈ over the conventional cascode LNA without the linearizing circuit.
TL;DR: In this article, a simple method is introduced to find the carrier lifetime variations with the measured conductivity and conductivity modulation under dark and gamma irradiation conditions, which enables us to give an improved wafer evaluation, processing and quality control in the field of photovoltaic materials and other electronic devices.
Abstract: The measurement of dark σ D , gamma-induced σ γ conductivities and the expected conductivity modulation Δσ in silicon wafers/samples is studied for developing a new technique for carrier lifetime evaluation. In this paper a simple method is introduced to find the carrier lifetime variations with the measured conductivity and conductivity modulation under dark and gamma irradiation conditions. It will be concluded that this simple method enables us to give an improved wafer evaluation, processing and quality control in the field of photovoltaic materials and other electronic devices.
TL;DR: In this paper, the authors proposed a new p?/n? gate locally separated channel (LSC) bulk FinFET which has vertically formed oxide region in the center of fin body.
Abstract: We proposed a new p?/n? gate locallyseparated- channel (LSC) bulk FinFET which has vertically formed oxide region in the center of fin body, and device characteristics were optimized and compared with that of normal channel (NC) FinFET. Key device characteristics were investigated by changing length of n ? poly-Si gate (L s ), the material filling the trench, and the width and length of the trench at a given gate length (L g ). Using 3-dimensional simulations, we confirmed that short-channel effects were properly suppressed although the fin width was the same as that of NC device. The LSC device having the trench non-overlapped with the source/drain diffusion region showed excellent I off suitable for sub-50 nm DRAM cell transistors. Design of the LSC devices were performed to get reasonable L s /L g and channel fin width (W cfin ) at given L g s of 30 ㎚, 40 ㎚, and 50 ㎚.
TL;DR: In this paper, a latchup-free design based on the lateral diffused MOS (LDMOS) adopting the "Darlington" approaches was designed, which reduced the size of the circuit when compared to the conventional inverter driven RC-triggered MOSFET ESD power clamp circuits.
Abstract: A latchup-free design based on the lateral diffused MOS (LDMOS) adopting the "Darlington" approaches was designed. The use of Darlington configuration as the trigger circuit results in the reduction of the size of the circuit when compared to the conventional inverter driven RC-triggered MOSFET ESD power clamp circuits. The proposed clamp was fabricated using a 0.35 μm 60V BCD (Bipolar CMOS DMOS) process and the performance of the proposed clamp was successfully verified by TLP (Transmission Line Pulsing) measurements.
TL;DR: The memory characteristics of the MOSFET were investigated and it was observed that the charge retention time of a double-stacked Si nanocluster MOSfET was longer than that of a single-layer device.
Abstract: We have studied nonvolatile memory properties of MOSFETs with double-stacked Si nanoclusters in the oxide-gate stacks. We formed Si nanoclusters of a uniform size distribution on a 5 nm-thick tunneling oxide layer, followed by a 10 nm-thick intermediate oxide and a second layer of Si nanoclusters by using LPCVD system. We then investigated the memory characteristics of the MOSFET and observed that the charge retention time of a double-stacked Si nanocluster MOSFET was longer than that of a single-layer device. We also found that the double-stacked Si nanocluster MOSFET is suitable for use as a dual-bit memory.
TL;DR: In this paper, a fully integrated inductorless CMOS impulse radio ultra-wideband (IR-UWB) receiver is implemented using 0.18 ㎛ CMOS technology for 3-5 ǫ application.
Abstract: A fully integrated inductorless CMOS impulse radio ultra-wideband (IR-UWB) receiver is implemented using 0.18 ㎛ CMOS technology for 3-5 ㎓ application. The UWB receiver adopts the non-coherent architecture, which removes the complexity of RF architecture and reduces power consumption. The receiver consists of inductorless differential three stage LNA, envelope detector, variable gain amplifier (VGA), and comparator. The measured sensitivity is -70 ㏈m in the condition of 5 Mbps and BER of 10?³. The receiver chip size is only 1.8 ㎜ × 0.9 ㎜. The consumed current is 15 ㎃ with 1.8 V supply.
TL;DR: In this paper, a new bit error rate (BER) simulator, Samsung BER simulator (SBERS), was developed to evaluate the link compliance and all kinds of effects of link compliance in a real environment.
Abstract: This paper is related to developing new Bit Error Rate (BER) simulator, Samsung BER simulator (SBERS), in order to evaluate the link compliance and all kinds of effects of link compliance in a real environment. SBERS allows to generate transmit pulse accurately by using the various parameters, and obtain the eye diagram and bathtub curve, which represents the performance of link, by calculating the transmit pulse and the measured frequency response characteristics. SBERS give results as same as real environment after taking account of distribution and value of noise. To verify the accuracy of simulator, we derive the simulated and measured result and compare eye opening. The difference came out to be within 5% error. It is possible to estimate the real environment and design the transmitter and receiver circuit effectively using new BER simulator, SBERS.
TL;DR: In this article, a scaling theory for dual material surrounding gate (DMSGT) MOSFETs is presented, which gives a guidance for the device design and maintaining a precise sub-reshold factor for given device parameters.
Abstract: In this Paper, we present a scaling theory for dual material surrounding gate (DMSGTs) MOSFETs, which gives a guidance for the device design and maintaining a precise subthreshold factor for given device parameters. By studying the subthreshold conducting phenomenon of DMSGTs, the effective conductive path effect (ECPE) is employed to acquire the natural length to guide the design. With ECPE, the minimum channel potential is used to monitor the subthreshold behavior. The effect of ECPE on scaling factor significantly improves the subthreshold swing compared to conventional scaling rule. This proposed model offers the basic designing guidance for dual material surrounding gate MOSFETs.
TL;DR: In this paper, a 2D analytical model for the threshold voltage on dual material surrounding gate (DMSG) MOSFETs is presented, where the parabolic approximation technique is used to solve the 2D Poisson equation with suitable boundary conditions.
Abstract: A new two dimensional (2-D) analytical model for the Threshold Voltage on dual material surrounding gate (DMSG) MOSFETs is presented in this paper. The parabolic approximation technique is used to solve the 2-D Poisson equation with suitable boundary conditions. The simple and accurate analytical expression for the threshold voltage and subthreshold swing is derived. It is seen that short channel effects (SCEs) in this structure is suppressed because of the perceivable step in the surface potential which screens the drain potential. We demonstrate that the proposed model exhibits significantly reduced SCEs, thus make it a more reliable device configuration for high speed wireless communication than the conventional single material surrounding gate (SMSG) MOSFETs.
TL;DR: In this article, the effect of physicochemical properties of solvents on the microstructure of polyvinyl carbazole (PVK) film for non-volatile polymer memory was investigated.
Abstract: The effect of physicochemical properties of solvents on the microstructure of polyvinyl carbazole (PVK) film for non-volatile polymer memory was investigated. For the solubilization of PVK molecules and the preparation of PVK films, four solvents with different physicochemical properties of the Hildebrand solubility parameter and vapor pressure were considered: chloroform, tetrahydrofuran (THF), 1,1,2,2-tetrachloroethane (TCE), and N,N-dimehtylformamide (DMF). The solubility of PVK molecules in the solvents was observed by ultraviolet-visible spectroscopy. PVK molecules were observed to be more soluble in chloroform, with a low Hildebrand solubility parameter, than solvents with higher values. The aggregated size and micro-/nano-topographical properties of PVK films were characterized using optical and atomic force microscopes. The PVK film cast from chloroform exhibited enhanced surface roughness compared to that from TCE and DMF. It was also confirmed that the microstructure of PVK film has an effect on the performance of non-volatile polymer memory.
TL;DR: In this article, the authors investigated the electron mobility in undoped double-gate (DG) MOSFETs of different channel architectures: a relaxed-Si DG SOI, a strained-Si (sSi) DG SSOI (strained-Si-oninsulator, containing no SiGe layer), and a strained Si-on-SiGe-ON-insulator (SGOI) at 300K.
Abstract: Electron mobility has been investigated theoretically in undoped double-gate (DG) MOSFETs of different channel architectures: a relaxed-Si DG SOI, a strained-Si (sSi) DG SSOI (strained-Si-oninsulator, containing no SiGe layer), and a strained-Si DG SGOI (strained-Si-on-SiGe-on-insulator, containing a SiGe layer) at 300K. Electron mobility in the DG SSOI device exhibits high enhancement relative to the DG SOI. In the DG SGOI devices the mobility is strongly suppressed by the confinement of electrons in much narrower strained-Si layers, as well as by the alloy scattering within the SiGe layer. As a consequence, in the DG SGOI devices with thinnest strained-Si layers the electron mobility may drop below the level of the relaxed DG SOI and the mobility enhancement expected from the strained-Si devices may be lost.
TL;DR: In this paper, the drift velocity of electrons and holes in silicon inversion layers was measured and a technique for extracting effective carrier velocity based on the actual inversion charge measurement was used.
Abstract: Carrier velocity in the MOSFET channel is the main driving force for improved transistor performance with scaling. We report measurements of the drift velocity of electrons and holes in silicon inversion layers. A technique for extracting effective carrier velocity which is a more accurate extraction method based on the actual inversion charge measurement is used. This method gives more accurate result over the whole range of V ds , because it does not assume a linear approximation to obtain the inversion charge and it does not limit the range of applicable V ds . For a very short channel length device, the electron velocity overshoot is observed at room temperature in 37 ㎚ MOSFETs while no hole velocity overshoot is observed down to 36 ㎚. The electron velocity of short channel device was found to be strongly dependent on the longitudinal field.
TL;DR: In this article, a wideband power efficient 2.2 -4.9 GHz medium power amplifier (MPA) has been designed and fabricated using 0.8 ㎛ SiGe BiCMOS process technology.
Abstract: In this paper, a wideband power efficient 2.2 ㎓ - 4.9 ㎓ Medium Power Amplifier (MPA) has been designed and fabricated using 0.8 ㎛ SiGe BiCMOS process technology. Passive elements such as parallel-branch spiral inductor, metal-insulatormetal (MIM) capacitor and three types of resistors are all integrated in this process. This MPA is a two stage amplifier with all matching components and bias circuits integrated on-chip. A P1㏈ of 17.7 ㏈m has been measured with a power gain of 8.7 dB at 3.4 ㎓ with a total current consumption of 30 ㎃ from a 3 V supply voltage at 25 ℃. The measured 3 ㏈ bandwidth is 2.7 ㎓ and the maximum Power Added Efficiency (PAE) is 41%, which are very good results for a fully integrated Medium PA. The fabricated circuit occupies a die area of 1.7 ㎜ × 0.8 ㎜.
TL;DR: In this paper, the authors demonstrated the functional 512Mb PRAM with 90㎚ technology using several novel core circuits, such as metal-2 line based global row decoding scheme, PN-diode cells based BL discharge (BLDIS) scheme, and PMOS switch based column decoding scheme.
Abstract: Phase-change random access memory (PRAM) chip cell phase of amorphous state is rapidly changed to crystal state above 160 Celsius degree within several seconds during Infrared (IR) reflow. Thus, on-board programming method is considered for PRAM chip programming. We demonstrated the functional 512Mb PRAM with 90㎚ technology using several novel core circuits, such as metal-2 line based global row decoding scheme, PN-diode cells based BL discharge (BLDIS) scheme, and PMOS switch based column decoding scheme. The reverse-state standby current of each PRAM cell is near 10 pA range. The total leak current of 512Mb PRAM chip in standby mode on discharging state can be more than 5 mA. Thus in the proposed BLDIS control, all bitlines (BLs) are in floating state in standby mode, then in active mode, the activated BLs are discharged to low level in the early timing of the active period by the short pulse BLDIS control timing operation. In the conventional sense amplifier, the simultaneous switching activation timing operation invokes the large coupling noise between the VSAREF node and the inner amplification nodes of the sense amplifiers. The coupling noise at VSAREF degrades the sensing voltage margin of the conventional sense amplifier. The merit of the proposed sense amplifier is almost removing the coupling noise at VSAREF from sharing with other sense amplifiers.
TL;DR: Measurement results show that the PLL bandwidth and randomJitter (RJ) variations are well regulated and that the use of a differentially controlled dualpath VCO is important for deterministic jitter (DJ) performance.
Abstract: This paper describes bandwidth linearization techniques in phase-locked loop (PLL) design for common-clock serial link applications Utilizing a continuously tunable single-input dual-path LC VCO and a constant-gain phase detector, a proposed architecture is well suited to implementing PLLs that must be compliant with standards that specify minimum and maximum allowable bandwidths such as PCI Express Gen2 or FB-DIMM applications A prototype 475 to 61-㎓ PLL is implemented in 90-nm CMOS Measurement results show that the PLL bandwidth and random jitter (RJ) variations are well regulated and that the use of a differentially controlled dualpath VCO is important for deterministic jitter (DJ) performance
TL;DR: In this article, a 3-stage low noise amplifier (LNA) employing one co-source and two cascode stages is developed using 0.13 ㎛ CMOS process.
Abstract: A 77 ㎓ 3-stage low noise amplifier (LNA) employing one co㎜on source and two cascode stages is developed using 0.13 ㎛ CMOS process. To compensate for the low gain which is caused by lossy silicon substrate and parasitic element of CMOS transistor, positive feedback technique using parasitic inductance of bypass capacitor is adopted to cascode stages. The developed LNA shows gain of 7.2 ㏈, S11 of -16.5 ㏈ and S22 of -19.8 ㏈ at 77 ㎓. The return loss bandwidth of LNA is 71.6 to 80.9 ㎓ (12%). The die size is as small as 0.7 ㎜ × 0.8 ㎜ by using bias line as inter-stage matching networks. This LNA shows possibility of 77 ㎓ automotive RADAR system using 0.13 ㎛ CMOS process, which has advantage in cost compared to sub-100 ㎚ CMOS process.
TL;DR: In this article, a 58 ㎓ CMOS LC cross-coupled VCO (Voltage Controlled Oscillator) was fabricated in a 0.13-㎛ Si RF CMOS technology.
Abstract: Recently, the demand on ㎜-wave (millimeter-wave) applications has increased dramatically. While circuits operating in the ㎜-wave frequency band have been traditionally implemented in Ⅲ-V or SiGe technologies, recent advances in Si MOSFET operation speed enabled ㎜-wave circuits realized in a Si CMOS technology. In this work, a 58 ㎓ CMOS LC cross-coupled VCO (Voltage Controlled Oscillator) was fabricated in a 0.13-㎛ Si RF CMOS technology. In the course of the circuit design, active device models were modified for improved accuracy in the ㎜-wave range and EM (electromagnetic) simulation was heavily employed for passive device performance predicttion and interconnection parasitic extraction. The measured operating frequency ranged from 56.5 to 58.5 ㎓ with a tuning voltage swept from 0 to 2.3 V. The minimum phase noise of -96 ㏈c/㎐ at 5 ㎒ offset was achieved. The output power varied around -20 ㏈m over the measured tuning range. The circuit drew current (including buffer current) of 10 ㎃ from 1.5 V supply voltage. The FOM (Figure-Of-Merit) was estimated to be -165.5 ㏈c/㎐.
TL;DR: The present status of technical development of a highly scalable, high-speed non-volatile PCM is overviewed, along with solutions that are being pursued in terms of innovative device structures and fabrication technologies, new phase change materials, and new memory schemes.
Abstract: The present status of technical development of a highly scalable, high-speed non-volatile PCM is overviewed. Major technical challenges are described along with solutions that are being pursued in terms of innovative device structures and fabrication technologies, new phase change materials, and new memory schemes.
TL;DR: In this paper, a hybrid balun, realized in 0.18 ㎛ CMOS, achieves 2.8 ㏈ higher gain and 1.9 ㅈ lower noise figure than its passive counterpart only at a current consumption of 0.67 㒃 from 1.2 V supply.
Abstract: A novel compact model for a five-port transformer balun is proposed for the efficient circuit design of hybrid balun. Compared to the conventional model, the proposed model provides much faster computation time and more reasonable values for the extracted parameters. The hybrid balun, realized in 0.18 ㎛ CMOS, achieves 2.8 ㏈ higher gain and 1.9 ㏈ lower noise figure than its passive counterpart only at a current consumption of 0.67 ㎃ from 1.2 V supply. By employing the hybrid balun, a differential zero-IF receiver is designed in 0.18 ㎛ CMOS for IEEE 802.15.4 ZigBee applications. It is composed of a differential cascode LNA, passive mixers, and active RC filters. Comparative investigations on the three receiver designs, each employing the hybrid balun, a simple transformer balun, and an ideal balun, clearly demonstrate the advantages of the hybrid balun in fully differential CMOS RF receivers. The simulated results of the receiver with the hybrid balun show 33 ㏈ of conversion gain, 4.2 ㏈ of noise figure with 20 ㎑ of 1/f noise corner frequency, and -17.5 ㏈m of IIP3 at a current consumption of 5 ㎃ from 1.8 V supply.
TL;DR: In this paper, an X-band MMIC power amplifier for radar application is developed using 0.25-μm gate length GaAs pHEMT technology and a bus-bar power combiner at output stage is used to minimize the combiner size and to simplify bias network.
Abstract: An X-band MMIC power amplifier for radar application is developed using 0.25-μm gate length GaAs pHEMT technology. A bus-bar power combiner at output stage is used to minimize the combiner size and to simplify bias network. The fabricated power amplifier shows 38.75 dBm (7.5 Watt) Psat at 10 GHz. The chip size is 3.5 mm × 3.9 mm.