Proceedings ArticleDOI
A “DOGLEG” channel router
David N. Deutsch
- pp 111-119
TLDR
The routing algorithm presented here was developed as part of LTX, a computer-aided design system for integrated circuit layout and was implemented on an HP-2100 minicomputer.Abstract:
This paper presents an algorithm for interconnecting two sets of terminals across an intervening channel. It is assumed that the routing is done on two distinct levels with all horizontal paths being assigned to one level and all vertical paths to the other. Connections between the levels are made through contact windows. A single net may result in many horizontal and vertical segments. Experimental results indicate that this algorithm is very successful in routing channels that contain severe constraints. Usually, the routing is accomplished within one track of the mathematical lower bound. The routing algorithm presented here was developed as part of LTX, a computer-aided design system for integrated circuit layout and was implemented on an HP-2100 minicomputer. A typical channel (300 terminals, 100 nets) can be routed in less than 5 seconds. Routing results are presented both for polycell chips under development at Bell Laboratories and for examples that exist in the published literature. For the latter, reductions of 10% in the wiring area were typical.read more
Citations
More filters
Journal ArticleDOI
The NP-completeness column: An ongoing guide
TL;DR: This is the fourteenth edition of a quarterly column that provides continuing coverage of new developments in the theory of NP-completeness, and readers who have results they would like mentioned (NP-hardness, PSPACE- hardness, polynomialtime-solvability, etc.), or open problems they wouldlike publicized, should send them to David S. Johnson.
Journal ArticleDOI
Efficient Algorithms for Channel Routing
Takeshi Yoshimura,Ernest S. Kuh +1 more
TL;DR: Two new algorithms merge nets instead of assigning horizontal tracks to individual nets to route a specified net list between two rows of terminals across a two-layer channel in the layout design of LSI chips.
Journal ArticleDOI
A Procedure for Placement of Standard-Cell VLSI Circuits
A.E. Dunlop,B.W. Kernighan +1 more
TL;DR: A method of automatic placement for standard cells (polycells) that yields areas within 10-20 percent of careful hand placements is described, based on graph partitioning to identify groups of modules that ought to be close to each other.
Proceedings ArticleDOI
A "Greedy" Channel Router
TL;DR: A new, “greedy”, channel-router that always succeeds, usually using no more than one track more than required by channel density, and may be forced in rare cases to make a few connections "off the end” of the channel.
Journal ArticleDOI
Hierarchical Wire Routing
M. Burstein,Richard Pelavin +1 more
TL;DR: A new approach to automatic wire routing of VLSI chips which is applicable to interconnection problem in uniform structures such as gate arrays, switchboxes, channels and is inherently fast, usually by an order of magnitude faster than the routers based on wave propagation (maze running) technique.
References
More filters
Journal ArticleDOI
An Algorithm for Path Connections and Its Applications
TL;DR: The algorithm described in this paper is the outcome of an endeavor to answer the following question: Is it possible to find procedures which would enable a computer to solve efficiently path-connection problems inherent in logical drawing, wiring diagramming, and optimal route finding?
Proceedings ArticleDOI
Wire routing by optimizing channel assignment within large apertures
TL;DR: The purpose of this paper is to introduce a new wire routing method for two layer printed circuit boards based on the newly developed channel assignment algorithm and requires many via holes.
Proceedings ArticleDOI
A solution to line routing problems on the continuous plane
TL;DR: A new line-routing algorithm based on the continuous plane, which is much faster than the conventional method and has given good results when applied to many line- routing problems such as mazes, printed circuit boards, substrates, and PERT diagrams.
Proceedings ArticleDOI
An optimum channel-routing algorithm for polycell layouts of integrated circuits
TL;DR: The algorithm, although based on branch and bound, has provided optimum routings for circuits with 50 to 60 nets in a minute or two of computing.
Proceedings ArticleDOI
LTX-A system for the directed automatic design of LSI circuits
TL;DR: LTX is a minicomputer-based design system for large-scale integrated circuit chip layout which offers a flexible set of interactive and automatic procedures for translating a circuit connectivity description into a finished mask design.