Journal ArticleDOI
Efficient Algorithms for Channel Routing
Takeshi Yoshimura,Ernest S. Kuh +1 more
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TLDR
Two new algorithms merge nets instead of assigning horizontal tracks to individual nets to route a specified net list between two rows of terminals across a two-layer channel in the layout design of LSI chips.Abstract:
In the layout design of LSI chips, channel routing is one of the key problems. The problem is to route a specified net list between two rows of terminals across a two-layer channel. Nets are routed with horizontal segments on one layer and vertical segments on the other. Connections between two layers are made through via holes. Two new algorithms are proposed. These algorithms merge nets instead of assigning horizontal tracks to individual nets. The algorithms were coded in Fortran and implemented on a VAX 11/780 computer. Experimental results are quite encouraging. Both programs generated optimal solutions in 6 out of 8 cases, using examples in previously published papers. The computation times of the algorithms for a typical channel (300 terminals, 70 nets) are 1.0 and 2.1 s, respectively.read more
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Algorithms for VLSI Physical Design Automation
TL;DR: This book is a core reference for graduate students and CAD professionals and presents a balance of theory and practice in a intuitive manner.
Proceedings ArticleDOI
A "Greedy" Channel Router
TL;DR: A new, “greedy”, channel-router that always succeeds, usually using no more than one track more than required by channel density, and may be forced in rare cases to make a few connections "off the end” of the channel.
Journal ArticleDOI
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TL;DR: A new approach to automatic wire routing of VLSI chips which is applicable to interconnection problem in uniform structures such as gate arrays, switchboxes, channels and is inherently fast, usually by an order of magnitude faster than the routers based on wave propagation (maze running) technique.
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Proceedings ArticleDOI
Minimum crosstalk channel routing
TL;DR: A new approach is proposed to the gridded channel routing problem which utilizes existing channel routing algorithms and improves upon the routing results by permuting the routing tracks.
References
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Journal ArticleDOI
Representation of a finite graph by a set of intervals on the real line
C. Lekkeikerker,J. Boland +1 more
Proceedings ArticleDOI
Wire routing by optimizing channel assignment within large apertures
TL;DR: The purpose of this paper is to introduce a new wire routing method for two layer printed circuit boards based on the newly developed channel assignment algorithm and requires many via holes.
Proceedings ArticleDOI
A “DOGLEG” channel router
TL;DR: The routing algorithm presented here was developed as part of LTX, a computer-aided design system for integrated circuit layout and was implemented on an HP-2100 minicomputer.
Journal ArticleDOI
One-dimensional logic gate assignment and interval graphs
TL;DR: A graph-theoretic approach to the design of one-dimensional logic gate arrays using MOS or I^{2}L units and it is shown that the number of tracks required for between-gate wiring is equal to the clique number (chromatic number) of H, and hence the optimum placement problem is converted to that of minimumClique number augmentation.
Proceedings ArticleDOI
An optimum channel-routing algorithm for polycell layouts of integrated circuits
TL;DR: The algorithm, although based on branch and bound, has provided optimum routings for circuits with 50 to 60 nets in a minute or two of computing.