A fast tally structure and applications to signal processing

TLDR: The design, layout, and simulation of a recursively defined VLSI chip is described, using a constraint-based, procedural layout language, and the results verify the expected asymptotic behavior of the implementation as a function of B.

Abstract: We describe the design, layout, and simulation of a recursively defined VLSI chip, using a constraint-based, procedural layout language. We use as an example the problem of counting the number of 1's in a set of (B - 1) input bits, where B is a power of 2. A regular, recursive structure, called a unary-to-binary converter (UBC(B)), tally circuit, or parallel counter, is described, based on the original design of Swartzlander. Area from the CIF plots and worst-case delay from simulations are given for 5 instantiations of the circuit, for B = 4, 8, 16, 32, and 64. The results verify the expected asymptotic behavior of the implementation as a function of B. The high-level, procedural approach leads to a succinct and parameterized description of the circuit. Verification and simulation of different versions of the circuit is much easier than with the conventional, hand-layout approach.