Proceedings ArticleDOI
A high I/O reconfigurable crossbar switch
Steven P. Young,P. Alfke,C. Fewer,S. McMillan,B. Blodget,D. Levi +5 more
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TLDR
A crossbar switch with 928 inputs and 928 outputs is presented, which yields a 16/spl times/ improvement in logic density compared with using conventional logic and uses partial configuration to modify routing resources during operation.Abstract:
A crossbar switch with 928 inputs and 928 outputs is presented. Switching elements are constructed using logic in the routing fabric. This approach yields a 16/spl times/ improvement in logic density compared with using conventional logic. Normally, the routing is fixed. However, in FPGAs (field programmable gate arrays), the interconnection is defined by the state of SRAM configuration cells, which are dynamically modifiable. Therefore, the switch is implemented on an FPGA using partial configuration to modify routing resources during operation. All paths are synchronously clocked at 155.5 MHz, creating a total throughput of 144.3 Gbits/s. to maintain constant clock latency across all paths, partially configurable delay registers are used. Finally, the partial reconfiguration controller is implemented in hardware to enable fast switch updates.read more
Citations
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Book ChapterDOI
A Self-reconfiguring Platform
TL;DR: In this article, a self-reconfiguring platform for FPGAs to dynamically reconfigure itself under the control of an embedded microprocessor has been reported and implemented on Xilinx Virtex IItm and Virtex II Protm devices.
Patent
Method for efficient inter-processor communication in an active-active RAID system using PCI-express links
TL;DR: In this paper, a fault-tolerant RAID system with redundant RAID controllers coupled by a PCI-Express link is described. But it is not shown how the PCI-express controller interprets a predetermined bit in the header as an interrupt request flag, rather than as its standard function specified by the PCIExpress specification.
Patent
Redundant storage controller system with enhanced failure analysis capability
TL;DR: In this paper, a redundant storage controller system that robustly provides failure analysis information (FAI) to an operator of the system is disclosed, which includes first and second storage controllers in communication with one another, such as via a PCI-Express link.
Patent
RAID system for performing efficient mirrored posted-write operations
TL;DR: In this paper, a bus bridge on a primary RAID controller receives user write data from a host and writes the data to its write cache and also broadcasts the data over a high speed link (e.g., PCI-Express) to a secondary RAID controller's bus bridge.
Patent
Broadcast bridge apparatus for transferring data to redundant memory subsystems in a storage controller
TL;DR: In this article, a bus bridge for broadcasted writes to redundant memory subsystems in a network storage controller is described, which includes a target that receives a write command on a first PCI-X bus on one side of the bridge.
References
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Proceedings ArticleDOI
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Proceedings Article
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