Journal ArticleDOI
A Highly Routable ULM Gate Array and Its Automated Customizaton
TLDR
This paper describes the design of a new functional-cell gate-array with inherently high routability, and its automated customization software which achieves 100 percent first-time routing.Abstract:
This paper describes the design of a new functional-cell gate-array with inherently high routability, and its automated customization software which achieves 100 percent first-time routing. Emphasis is placed upon the considerations which influence the selection of a functional array primitive. A highly structured interconnection architecture will be described, which employs interdigitating cell terminals in a polycell-like wiring channel topology to simplify the routing procedure for the array. The detailed structure and operation of an automatic customization software package is discussed. This package, developed specially for the array, utilizes the structured topology to achieve track densities which are comparable with those produced by state-of-the-art algorithms. This array has been fabricated, in a CMOS technology, as a test-vehicle for both the unusual topology and the unique functional cells. Throughout the study, emphasis has been placed on achieving a coherent strategy for producing efficiently routed gate-arrays with the minimum of sophisticated design tools. Examples will be cited to show that this methodology is economical both in the rapidity with which finished designs may be produced, and in its utilization of silicon-area.read more
Citations
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Journal ArticleDOI
Integrating UAHPL-DA systems with VLSI design tools to support VLSI DA courses
TL;DR: A complete operational environment established with the help of state-of-the-art tools, to support courses in design automation (DA) of VLSI circuits, is described, which is excellent for teaching and research at universities.
Proceedings ArticleDOI
Design for variability in CMOS logic circuits: Uncommitted motif arrays (UMAs)
TL;DR: This work proposes the use of uncommitted arrays of digital sub-blocks, motifs, as the basic building block for CMOS logic, to maximize functional flexibility, minimize routing complexity, and increase tolerance to systematic variability.
References
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Journal ArticleDOI
On a Pin Versus Block Relationship For Partitions of Logic Graphs
B.S. Landman,R.L. Russo +1 more
TL;DR: Partitions of the set of blocks of a computer logic graph, also called a block graph, into subsets called modules demonstrate that a two-region relationship exists between P, the average number of pins per module, and B, theaverage number of blocks per module.
Proceedings ArticleDOI
Wire routing by optimizing channel assignment within large apertures
TL;DR: The purpose of this paper is to introduce a new wire routing method for two layer printed circuit boards based on the newly developed channel assignment algorithm and requires many via holes.
Journal ArticleDOI
Efficient Algorithms for Channel Routing
Takeshi Yoshimura,Ernest S. Kuh +1 more
TL;DR: Two new algorithms merge nets instead of assigning horizontal tracks to individual nets to route a specified net list between two rows of terminals across a two-layer channel in the layout design of LSI chips.
Proceedings ArticleDOI
A "Greedy" Channel Router
TL;DR: A new, “greedy”, channel-router that always succeeds, usually using no more than one track more than required by channel density, and may be forced in rare cases to make a few connections "off the end” of the channel.
Journal ArticleDOI
Connectivity of Random Logic
TL;DR: This paper develops a relation between the partitioning properties of computer logic and the distribution of connection lengths and finds that an exponential partitioning function leads to an inverse power law length distribution.