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A New Selection Strategy for On-Chip Networks

TLDR
The proposed approach introduces the concept of neighbors-on-path to exploit the situations of indecision occurring when the routing function returns several admissible output channels to improve the performance with a minimal overhead on area and energy consumption.
Abstract
Efficient and deadlock-free routing is critical to the performance of networks-on-chip. In this paper we present an approach that can be coupled to any adaptive routing algorithm to improve the performance with a minimal overhead on area and energy consumption. The proposed approach introduces the concept of Neighbors-on-Path to exploit the situations of indecision occurring when the routing function returns several admissible output channels. A selection strategy is developed with the aim to choose the channel that will allow the packet to be routed to its destination along a path that is as free as possible of congested nodes. Performance evaluation is carried out by using a flit-accurate simulator on traffic scenarios generated by both synthetic and real applications. Results obtained show how the proposed selection policy applied to the Odd-Even routing algorithm outperforms other deterministic and adaptive routing algorithms both in average delay and energy consumption.

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Citations
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Journal ArticleDOI

Cycle-Accurate Network on Chip Simulation with Noxim

TL;DR: Noxim is presented, an open, configurable, extendible, cycle-accurate NoC simulator developed in SystemC, which allows to analyze the performance and power figures of both conventional wired NoC and emerging WiNoC architectures.
Journal ArticleDOI

Networks on chips: structure and design methodologies

TL;DR: Several common architectures and prevalent techniques that can deal well with the design issues of communication performance, power consumption, signal integrity, and system scalability in an NoC are discussed and a novel bidirectional NoC (BiNoC) architecture is proposed to break the conventional performance bottleneck caused by bandwidth restriction in conventional NoCs.
Journal ArticleDOI

Region-Based Routing: A Mechanism to Support Efficient Routing Algorithms in NoCs

TL;DR: The proposed region-based routing (RBR) mechanism which groups destinations into network regions allowing an efficient implementation with logic blocks and shows that the number of entries in the table is significantly reduced, especially for large networks.
Journal ArticleDOI

Topology-Aware Adaptive Routing for Nonstationary Irregular Mesh in Throttled 3D NoC Systems

TL;DR: A Topology Aware Adaptive Routing (TAAR) to balance the traffic load for NSI-Mesh in 3D NoC and according to the proposed VLSI architecture, the TAAR only needs less than 24.8 percent hardware overhead.
Proceedings ArticleDOI

Traffic-and thermal-aware routing for throttled three-dimensional Network-on-Chip systems

TL;DR: An adaptive routing algorithm, Traffic- and Throttling-Awareness Routing (TTAR), is proposed to address the traffic congestion due to throttling of transient-temperature control and can achieve 8% ∼ 680% throughput improvements than the previous routing algorithms at 50-cycle average latency.
References
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Proceedings ArticleDOI

Route packets, not wires: on-chip interconnection networks

TL;DR: This paper introduces the concept of on-chip networks, sketches a simple network, and discusses some challenges in the architecture and design of these networks.
Proceedings ArticleDOI

A network on chip architecture and design methodology

TL;DR: A packet switched platform for single chip systems which scales well to an arbitrary number of processor like resources which is the onchip communication infrastructure comprising the physical layer, the data link layer and the network layer of the OSI protocol stack.
Journal ArticleDOI

The odd-even turn model for adaptive routing

TL;DR: Simulation results show that the even adaptiveness provided by the odd-even turn model makes message routing less vulnerable to nonuniform factors such as hot spot traffic and results in a smaller fluctuation of the network performance with respect to different traffic patterns.
Journal ArticleDOI

Energy- and performance-aware mapping for regular NoC architectures

TL;DR: An algorithm which automatically maps a given set of intellectual property onto a generic regular network-on-chip (NoC) architecture and constructs a deadlock-free deterministic routing function such that the total communication energy is minimized.
Proceedings ArticleDOI

DyAD - smart routing for networks-on-chip

TL;DR: A new routing technique which judiciously switches between deterministic and adaptive routing based on the network's congestion conditions is envisioned, and the effectiveness of DyAD is evaluated by comparing it with purely deterministicand adaptive routing schemes under different traffic patterns.