Delft University of Technology
A Power-Efficient Readout for Wheatstone-Bridge Sensors With COTS Components
Jiang, Hui; Vogel, Johan G.; Nihtianov, Stoyan
DOI
10.1109/JSEN.2017.2755074
Publication date
2017
Document Version
Accepted author manuscript
Published in
IEEE Sensors Journal
Citation (APA)
Jiang, H., Vogel, J. G., & Nihtianov, S. (2017). A Power-Efficient Readout for Wheatstone-Bridge Sensors
With COTS Components.
IEEE Sensors Journal
,
17
(21), 6986-6994.
https://doi.org/10.1109/JSEN.2017.2755074
Important note
To cite this publication, please use the final published version (if applicable).
Please check the document version above.
Copyright
Other than for strictly personal use, it is not permitted to download, forward or distribute the text or part of it, without the consent
of the author(s) and/or copyright holder(s), unless the work is under an open content license such as Creative Commons.
Takedown policy
Please contact us and provide details if you believe this document breaches copyrights.
We will remove access to the work immediately and investigate your claim.
This work is downloaded from Delft University of Technology.
For technical reasons the number of authors shown on this cover page is limited to a maximum of 10.
Abstract— This paper presents a direct digital converter for
Wheatstone bridge sensors which is realized with commercial
off-the-shelf (COTS) components. The power efficiency of the
readout is enhanced by embedding the bridge sensor in a
second-order Continuous-Time Sigma-Delta Modulator
(CTΔΣM). By directly digitizing the output signal of a Wheatstone
bridge in the current mode, the noise performance is dominated
by the operational amplifier (Opamp) in the first integrator and
the bridge sensor. To demonstrate the performance of the
proposed circuit, a MEMS Piezoresistive Differential Pressure
(MPDP) sensor is used. Measurement results show a resolution of
12.7 mPa
rms
(0.41 mΩ
rms
), with a 0.5 ms conversion time, can be
achieved. Powered by 5 V, the circuit and the bridge sensor draws
9.55 mW and 7.58 mW, respectively.
Index Terms—Direct digital converter, bridge sensor readout,
Continuous-Time Sigma-Delta Modulator, mPa-level differential
pressure sensing.
I. INTRODUCTION
EC
ENTLY, digital converters that can directly convert
physical values of sensors into digital values have become
increasingly more attractive for many low-power and
energy-constrained applications. Some examples are:
capacitance-to-digital converters (CDCs), inductance-to-digital
converters (IDCs), and resistance-to-digital converters (RDCs)
[1-3]. Most of the reported solutions are based on
application-specific integrated circuits (ASICs) as they offer
energy efficiency and small footprints. However, in many
industrial applications, such as precision mechatronic systems
used in manufacturing [4], only a limited number of high
performance sensors are needed. The use of ASICs increases
cost, while available off-the-shelf circuits cannot always
provide the required performance. Therefore, the alternative is
to design a readout circuit using commercial off-the-shelf
(COTS) components.
This paper presents a power-efficient COTS-based direct
digital converter for precision mechatronic systems which
detects differential pressure with 15 mPa
rms
resolution [4]. To
facilitate use in the feedback of a fast servo loop for pressure
control, the direct digital converter requires a 0.5 ms
conversion time [4]. Furthermore, the power consumption of
the direct digital converter should be less than 20 mW to
minimize the self-heating of the electronics.
Owing to their high sensitivity, piezoresistive differential
pressure sensors are commonly embedded in Wheatstone
bridges to measure ultra-low differential pressure. An example
of such a sensor is the AC4010 from Acuity Inc. (Fig. 1a),
which senses differential pressure p
1
– p
2
by measuring the
deflection of a silicon membrane with high piezoresistivity
(Fig. 1b) [5]. With four piezoresistors connected in a full
Wheatstone bridge, the sensitivity is quadrupled.
Fig. 1. (a) MEMS piezoresistive differential pressure sensor; (b)
Piezoresistors that can be used in a full Wheatstone bridge configuration.
Conventionally, the bridge sensor is operated in voltage
mode with an Instrumentation Amplifier (IA) that amplifies the
output voltage of the bridge [6]. These readout methods consist
of two main parts: an IA and an Analog-to-Digital Converter
(ADC), as shown in Fig. 2a. An IA is typically designed with a
high input impedance and a large accurate gain to boost the
signal amplitude of the sensor outputs and to drive the
succeeding ADC stage, which converts the results into digital
code. This results in readout involving two local feedback
loops to guarantee precision (IA and ADC) (Fig. 2a), with an
overall open loop gain that far exceeds the necessary closed
loop gain. However, this readout has lower energy efficiency,
since an IA consists of at least two operational amplifiers
(Opamps), in case high resolution has to be achieved, which
dominates the power dissipation readout [7 - 9].
To address these issues, an alternative readout topology has
been proposed in the literature (Fig. 2b) [10, 11]. It embeds the
IA and the ADC in one closed loop to improve energy
efficiency and reduce complexity. In this architecture, one
feedback loop is implemented using an indirect current
feedback network. The high input impedance of the readout ICs
is realized using Gm-C integrators. However, additional design
effort is needed to accommodate the poor linearity of the Gm-C
integrators, resulting in a large area [11]. Furthermore,
applying this architecture with COTS components is difficult as
a very good match is required between the G1 and G2 stages to
avoid thermal drift. Lastly, the energy efficiency of the readout
A Power-Efficient Readout for
Wheatstone-Bridge Sensors with COTS
Components
Hui Jiang, Student Member, IEEE, Johan G. Vogel, Member, IEEE,
and Stoyan Nihtianov, Senior Member, IEEE
R
© 2017 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or
future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works,
for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.
is still limited by these two Gm stages.
(
a)
Vdd
R+r
R-r
R-r
ADC
R+r
A1
A2
μC
Vdd
R+r
R-r
R-r
R+r
μC
Quantizer
DAC
G1
G2
(b)
Fig. 2. Typical readout solution for the bridge sensor: (a) Two-loop topology;
(b) Single-loop topology.
In comparison, capacitively coupled IAs (CCIAs) provide
even better energy efficiency because they only have a single
main Opamp which dominates the noise and power dissipation
of the readout circuit of the bridge sensors [12]. However, an
energy-efficient CCIA is also difficult to realize using COTS
components on a PCB board, since the noise performance will
be degraded by the PCB board parasitic [13].
Reading the Wheatstone bridge in the current mode is a
promising approach to avoid the shortcomings of the voltage
mode readout approach and thus improve the energy efficiency
of the sensing system. Several studies on the current mode
readout using transimpedence amplifiers and current conveyors
have been reported [14, 15]. However, to obtain a digital output
from such an amplified signal, a Discrete-Time (DT) ADC with
an anti-aliasing filter or a high oversampling ratio is needed.
An optimized COTS-based current mode readout solution
that embeds the MPDP sensor into a second-order
Continuous-Time Sigma-Delta Modulator (CTΔΣM) which
does not require a high-order anti-aliasing filter, is proposed in
this paper. This solution simplifies the design of the readout
without compromising performance. The paper is organized as
follows. Section II discusses the operating principle of the
readout circuit. Section III provides details of the readout
architecture. The circuit implementation and COTS
components selection is discussed in Section IV. Section V
presents experimental results obtained using a prototype
readout with the MPDP sensor. Finally, Section VI presents
conclusions.
II. C
URRENT MODE OPERATION PRINCIPLE
Bridge sensors are usually read out in voltage mode, which
can, ideally, provide the best linearity performance. The output
V
out
of the Wheatstone bridge can be defined as:
out,bridge
Vdd r
V
R
×
=
,
(1)
where R is the bridge resistance and r is varying resistance.
However, as shown in Fig. 2a, two of the Opamps A1 and A2 in
a three-Opamp IA are typically located close to the bridge
sensors in the signal chain to provide high input impedance [4].
These two Opamps usually dominate the noise contribution of
the readout. To obtain better noise performance, more power
needs to be consumed by these two main amplifiers, which
consequently increases the power consumption of the readout.
The same statement is valid for indirect current-feedback IAs
(CFIAs), since the input and the feedback Gm stages are the
main noise sources of the readout [9].
Instead of reading the Wheatstone bridge in the voltage
mode, an alternative interfacing strategy with better energy
efficiency is to read out the output current of the Wheatstone
bridge with a Transimpedance Amplifier (TIA) [14], as shown
in Fig. 3a. The main noise contribution of this circuit comes
from a single main Opamp, because R
f
is significantly larger
than R. The output signal of the TIA can be defined as:
out,TIA f
22
2 Vdd r
VR
Rr
××
=
−
.
(2)
This shows that the output is a nonlinear function of r.
However, the additional nonlinearity due to the variation of r is
relatively small compared to the intrinsic nonlinearity of MPDP
sensors, since the ratio of r/R is smaller than 1%.
An additional benefit of MPDP sensors is that sensitivity can
be easily adjusted by tuning the feedback resistor R
f
, which will
accommodate the large spread in MPDP sensitivity.
bs
bs
+V
out
R
f
R
f
Vdd
−V
out
R+r
R+r
R-r
R-r
Opamp
(a)
R
f
R
f
Vdd
R+r
R+r
R-r
R-r
Loop filter
and
Comparator
(b)
Vdd
GND
GND
Vdd
Fig. 3. (a) Wheatstone bridge interface with analog feedback (TIA); (b)
Wheatstone bridge interface with digital feedback.
However, in practice, the frequency components in the TIA
outputs that are greater than half the sampling rate will alias
into the frequency band of interest during the analog-to-digital
conversion (ADC) when sampling type (discrete time – DT)
ADCs are used [16]. One possible solution is to use an
anti-aliasing filter before this ADC, e.g. a SAR ADC, to avoid
the impact of high-frequency noise and interference.
Especially, for Nyquist rate ADCs, a high-order anti-aliasing
filter is preferred for maintaining the gain accuracy around the
corner frequency of the filter. Another solution to avoid
aliasing is to use an oversampling ADC to relax the
requirement for the anti-aliasing filter. However, this
oversampling usually results in more power dissipation.
Alternatively, the analog resistive feedback network of the
TIA can be realized digitally by using the charge balancing
technique in a CT ΣΔ Modulator loop, as shown in Fig. 3b. Fig.
4 shows the readout approach, which is realized by embedding
the Wheatstone bridge into a first-order CT ΣΔ ADC. The DC
output current of the bridge sensor that is caused by differential
pressure will be injected into the virtual ground of the
integrator. In every clock cycle, the compensation current,
controlled by bs, attempts to balance the current from the
bridge. Therefore, in a long stream of zeros and ones, the
negative feedback loop will make sure the averaged output
voltage of the integrator is zero. By extracting the ratio of the
number of ones and the total number of clock cycles, the output
current of the Wheatstone bridge can be accurately obtained
[17].
C
int
C
int
R
f
R
f
f
s
bs
bs
bs
bs
bs
bs
Vdd
GND
Vdd
R+r
R+r
R-r
R-r
Fig. 4. Wheatstone bridge interface with a first-order CT ΣΔ ADC.
Compared to bridge readout based on DT ΣΔ Modulators,
readout based on CT ΣΔ Modulators has several advantages.
First, a CT ΣΔ Modulator is inherently anti-aliasing. Compared
to DT ΣΔ Modulators, CT ΣΔ Modulators postpone the
sampling process until the output of the loop filters.
Consequently, the noise folding occurs at the less sensitive
point of the loop. The absence of an anti-aliasing filter makes
CT ΣΔ Modulators more energy-efficient compared to their DT
counterparts [18]. Second, unlike a DT ΣΔ Modulator, which
requires a certain unity gain frequency of the Opamp in the loop
for a given clock frequency, the clock frequency of a CT ΣΔ
Modulator is limited by the regeneration time of the quantizer
and the update time of the feedback DAC. Thus, a CT ΣΔ
Modulator with a slower Opamp can achieve the same accuracy
as a DT ΣΔ Modulator, which has to employ relatively faster
Opamps in the loop; hence less power is required in a CT ΣΔ
Modulator given the trade-off between power and speed. Last
but not least, the switches in the CT ΣΔ Modulator are at low
impedance nodes, which simplifies the COTS-based design, as
COTS switches usually have a larger charge injection error.
III. R
EADOUT ARCHITECTURE
A. Topology
To guarantee the accuracy of the ΣΔ Modulator, a single-bit
DAC, which is inherently linear, has been chosen. Thus, the
quantizer can be realized using a comparator. In order to meet
the resolution specification of the bridge sensors with fewer
clock cycles, a higher-order ΣΔ modulator is preferable. Here,
the second-order topology is adopted for energy efficiency. The
oversampling ratio is set at 500 so that it can provide enough
quantization noise suppression for the target resolution.
c
2
c
1
+
+
DAC
A
B
s
ω
1
s
ω
2
f
s
u(t) y(t) v[n]
v(t)
Fig. 5. Feedforward second-order ΣΔ Modulator.
A second-order ΣΔ Modulator requires a certain type of
compensation provided by either a feedback structure or
feedforward structure to maintain its stability. A feedforward
structure is designed (Fig. 5) to simplify the feedback DAC,
since the feedback structure requires two feedback DACs. The
transfer function from A to B (Fig. 5) is given by:
2
12
()
B
AB
A
V
Hs c c
Vs
ω
→
= =+⋅
.
(3)
To optimize the Noise Transfer Function (NTF) of the ΣΔ
Modulator, we have chosen c
1
= 4 and c
2
=1. The first integrator
is realized by a current integrator with capacitive feedback. The
second integrator is an RC type in which the adder at node B is
realized by a differential amplifier with resistive feedback ( Fig.
6).
B. Noise Analysis
Because the out-of-band noise of ΣΔ Modulators is
eliminated by the digital decimation filter, only in-band noise
needs to be considered. Moreover, due to the inherent
anti-aliasing property of CT ΣΔ Modulators, sampling does not
increase the in-band noise [18]. The in-band noise of the
remaining loop filter is suppressed by the gain of the first
integrator when referred to the input. This allows the noise
contributed by the second integrator, adder, and comparator to
be negligible because of the high low-frequency gain of the
Opamp in the first integrator. Thus, the main noise contributors
are the bridge sensor, the Opamp in the first integrator, and the
DAC.
f
s
bs
C
int2
C
int2
C
int1
C
int1
R
1
R
1
Opamp
1
Vdd
R+r
R+r
R-r
R-r
Opamp
2
R
2
R
2
Opamp
3
R
4
R
4
R
3
R
3
V
A
V
A
V
B
V
B
Vdd
R
DAC
R
DAC
R 3.3 kΩ R
3
50 kΩ
r 33 Ω R
4
200 kΩ
R
DAC
200 kΩ C
int1
33 pF
R
1
100 kΩ C
int2
4 pF
R
2
200 kΩ f
s
2 MHz
Fig. 6. Schematic of the feedforward second-order ΣΔ Modulator.
C
int1
Opamp
V
A
R
1
i
n_B1
R
2
i
n_B2
Vdd
v(t)
R
DAC
i
n_DAC
i
n_A
v
n_A
i
n_total
z
Fig. 7. Noise analysis of the first integrator.
To simplify the analysis, a single-ended version of the loop
filter, as shown in Fig. 7, is used to derive the input-referred
noise of the CT ΣΔ Modulator. The input-referred noise power
at the virtual ground of the first integrator, which includes the
noise of the Wheatstone bridge, is given by:
2
_
2 22 2 2
_ _1 _2 _ _
nA
ntotal nB nB nDAC nA
DAC
v
i iii i
RRR
= + + + +
,
2
_
2 22
_ __
2
2
nA
n total n B n A
v
i ii
R
⋅
≈⋅ + +
,
(4)
where v
n_A
is the input-referred voltage noise, i
n_A
is the input
current noise of the amplifier in the first integrator, and
R=R
1
=R
2
. As shown in Eq. 4, the major noise source of this
readout circuit is the Opamp and the bridge sensor, since R
DAC
>> R. This suggests that the proposed architecture can be more
power-efficient compared to traditional voltage-mode readouts.
Moreover, the performance of the Opamp in the first integrator
is the key to the readout performance.
IV. I
MPLEMENTATION DETAILS
A PCB-level prototype that uses COTS components has been
implemented. In this design, the reference voltage of the
readout DAC is the same as the bridge biasing voltage.
Therefore, the effect of variation in the biasing voltage is
suppressed by the ratio-metric conversion. The noise, offset,
and non-linearity of the remaining CT ΣΔ Modulator are
suppressed by the gain of the first integrator. Hence, the Opamp
of the first integrator and the DAC are the most critical blocks
in this design.
A. Opamp of the First Integrator
The MPDP sensor has two main noise sources: thermal noise
and 1/f noise. The measured output current noise of the sensor
(AC4010, Acuity Incorporated) over 2 kHz of bandwidth is 325
pA when the biasing voltage of the sensor is 5 V. First, to
ensure that the resolution is defined by the current noise of the
sensor, the noise contribution of the readout should be lower of
the noise of the MPDP sensor. Second, an energy-efficient fully
differential Opamp is needed to minimize the self-heating
effect of the first integrator. Lastly, the input offset current drift
of the Opamp should be small.
The input offset current drift can be defined as:
