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Proceedings ArticleDOI

A Requests Bundling DRAM Controller for Mixed-Criticality Systems

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TLDR
A novel DRAM controller that bundles and executes memory requests of hard real-time applications in consecutive rounds based on their type to reduce read/write switching delay and provides a configurable, guaranteed bandwidth for soft real- time requests is designed.
Abstract
We design a novel DRAM controller that bundles and executes memory requests of hard real-time applications in consecutive rounds based on their type to reduce read/write switching delay. At the same time, our controller provides a configurable, guaranteed bandwidth for soft real-time requests. We show that there is a fundamental trade-off between the latency guarantee for hard real-time requests and the bandwidth provided to soft requests. Finally, we compare our approach analytically and experimentally with the current state-of-theart real-time memory controller for single-rank DRAM devices, which applies type reordering at the level of DRAM commands rather than requests. Our evaluation shows that for tasks exhibiting average row hit ratios, or for which computing a row hit guarantee might be difficult, our controller provides both smaller guaranteed latency and larger bandwidth.

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Citations
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Mixed Criticality Systems - A Review

TL;DR: This review covers research on the topic of mixed criticality systems that has been published since Vestal’s 2007 paper and covers the period up to and including December 2015.
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Bounding DRAM Interference in COTS Heterogeneous MPSoCs for Mixed Criticality Systems

TL;DR: This paper derives a generalized interference delay analysis for DRAM main memory that accounts for a breadth of features deployed in COTS platforms, and explores the design space by studying the effects of each feature on both the worst-case delay for critical applications, and the bandwidth for noncritical applications.
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References
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Proceedings ArticleDOI

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Journal ArticleDOI

An Analyzable Memory Controller for Hard Real-Time CMPs

TL;DR: An analyzable JEDEC-compliant DDRx SDRAM memory controller (AMC) for hard real-time CMPs is proposed, that reduces the impact of memory interferences caused by other tasks on WCET estimation, providing a predictable memory access time and allowing the computation of tight WCET estimations.
Proceedings ArticleDOI

Worst Case Analysis of DRAM Latency in Multi-requestor Systems

TL;DR: A novel, composable worst case analysis for DDR DRAM is presented that provides improved latency bounds compared to existing works by explicitly modeling the DRAM state and scales better with increasing number of requestors and memory speed.
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