Proceedings ArticleDOI
A Robust Hybrid CT/DT 0-2 MASH DSM with Passive Noise-Shaping SAR ADC
Ke Li,Sai-Weng Sin,Liang Qi,Weibing Zhao,Guoxing Wang,Rui P. Martins +5 more
- pp 551-555
TLDR
In this paper , a hybrid CT/DT0-2 multi-stage noise-shaping (MASH) delta-sigma modulator (DSM) with a passive noiseshaping successive approximation register (NSSAR) ADC was proposed.Abstract:
This paper presents a hybrid CT/DT0-2 multi-stage noise-shaping (MASH) delta-sigma modulator (DSM) with a passive noise-shaping successive approximation register (NSSAR) ADC as the $2^{\mathrm{n}\mathrm{d}}$ stage. The overall architecture is simple and robust. The front-end stage employs the continuous-time (CT) operation to perform coarse quantization and provide inherent anti-aliasing and easy driving. The back-end stage uses a second-order NS-SAR architecture, which excels at PVT robustness, power efficiency, and scaling friendliness. It also results in large relaxation of matching issues between the analog and the digital domains compared with conventional CT-MASH. Behavioral simulation results demonstrate the effectiveness and robustness of the proposed hybrid MASH architecture.read more
References
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Book
Understanding Delta-Sigma Data Converters
TL;DR: This chapter discusses the design and simulation of delta-sigma modulator systems, and some of the considerations for implementation considerations for [Delta][Sigma] ADCs.
Journal ArticleDOI
A 12-Bit, 10-MHz Bandwidth, Continuous-Time $\Sigma\Delta$ ADC With a 5-Bit, 950-MS/s VCO-Based Quantizer
M.Z. Straayer,Michael H. Perrott +1 more
TL;DR: The use of VCO-based quantization within continuous-time (CT) SigmaDelta analog-to-digital converter (ADC) structures is explored, with a custom prototype in 0.13 mum CMOS showing measured performance of 86/72 dB SNR/SNDR with 10 MHz bandwidth.
Proceedings Article
A 12-Bit, 10-MHz Bandwidth, Continuous-Time ΣΔ ADC With a 5-Bit, 950-MS/s VCO-Based Quantizer
M.Z. Straayer,Michael H. Perrott +1 more
TL;DR: The use of VCO-based quantization within continuous-time (CT) ΣΔ analog-to-digital converter (ADC) structures is explored, with a custom prototype in 0.13 μm CMOS showing measured performance of 86/72 dB SNR/SNDR with 10 MHz bandwidth.
Journal ArticleDOI
A 90-MS/s 11-MHz-Bandwidth 62-dB SNDR Noise-Shaping SAR ADC
TL;DR: This work introduces an oversampling, noise-shaping SAR ADC architecture that achieves 10-b ENOB with an 8-b SAR DAC array, thereby decoupling comparator noise from ADC performance.
Journal ArticleDOI
A 13-ENOB Second-Order Noise-Shaping SAR ADC Realizing Optimized NTF Zeros Using the Error-Feedback Structure
TL;DR: This paper presents a second-order NS-SAR ADC employing the error-feedback (EF) structure to realize complex NTF zeros for noise-shaping enhancement with the minimum modification to a standard SAR.