Proceedings ArticleDOI
A universal cyclic division circuit
Andrew W. Maholick,Richard B. Freeman +1 more
- pp 1-8
TLDR
This paper describes the design of a cyclic redundancy checking circuit using generalized systems containing more logic than the specialized systems used in the past, implemented in unit logic, and at even lower cost.Abstract:
Recent innovations in circuit technology have allowed design alternatives that previously would have been economically unsound. LSI technology permits the use of generalized systems containing more logic than the specialized systems used in the past, implemented in unit logic, and at even lower cost. Five years ago an engineer would not have even considered using a cyclic redundancy checking circuit in the manner described here.read more
Citations
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Journal ArticleDOI
High-speed parallel CRC circuits in VLSI
T.-B. Pei,C. Zukowski +1 more
TL;DR: It is shown that parallel architectures fall somewhat short of ideal speedups in practice, but they should still enable current CMOS technologies to go well beyond 1 Gb/s data rates.
Patent
Binary synchronous communications processor system and method
TL;DR: In this article, a communications processor system including a message switching digital computer is described, which is programmed to receive binary coded data from a plurality of communication control devices connected to communication lines.
Patent
High performance error control coding in channel encoders and decoders
TL;DR: In this paper, an improved error control coding scheme is implemented in low bit rate coders in order to improve their performance in the presence of transmission errors typical of the digital cellular channel.
Patent
Error check code recomputation method time independent of message length
Michael Gutman,Ping Dong +1 more
TL;DR: In this article, the authors propose a method of recomputing at the intermediate node a new error-check code for the altered message with a predetermined number of computational operations, independent of the length of the message.
Patent
Apparatus for detecting and correcting errors in an encoded memory word
TL;DR: In this article, a single and double error detection and correction system is presented for a digital memory system which performs single error detection, correction, and detection of faults in the memory storage elements which do not produce errors in the data word stored therein.
References
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Journal ArticleDOI
Cyclic Codes for Error Detection
W. W. Peterson,D. T. Brown +1 more
TL;DR: The potentialities of these codes for error detection and the equipment required for implementing error detection systems using cyclic codes are described in detail.
Journal ArticleDOI
Serial-to-Parallel Transformation of Linear-Feedback Shift-Register Circuits
M. Y. Hsiao,K. Y. Sih +1 more
TL;DR: An application of cyclic errorcorrecting codes in multiple-Parallel channels is studied and three methods are given to perform this serial-to-parallel transformation of linear feedback shiftI2 lJ2 register circuits.
Proceedings ArticleDOI
A multi-channel CRC register
TL;DR: The Cyclic Redundancy Check (CRC) is extremely efficient and well suited for error detection in transmission, retrieval or storage of variable length records of binary data.