Patent
Addressable shadow port and protocol for serial bus networks
TLDR
In this article, a protocol and associated circuitry operable for efficiently extending serial bus capability in system environments is described, and an example of application of the invention to a backplane system utilizing the IEEE standard serial bus is detailed.Abstract:
A protocol and associated circuitry operable for efficiently extending serial bus capability in system environments is described. The protocol is designed to coexist and be fully compatible with existing serial bus approaches, and in particular an example of application of the invention to a backplane system utilizing the 1149.1 IEEE standard serial bus is detailed. The circuitry and protocol required to couple any one of the boards on the backplane to the serial bus master without modifying the existing serial bus protocol, without adding additional signals, and without affecting the throughput rate of the serial bus is described. The invention advantageously allows the serial bus master to select, communicate with, and deselect backplane boards so that high level test functions may be simultaneously executed and monitored. Additional preferred embodiments are also described.read more
Citations
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Patent
System and method for communicating with an integrated circuit
TL;DR: In this paper, the authors present a system and method for communicating with an integrated circuit that allows the integrated circuit to communicate debugging information and system bus transaction information with an external system.
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Patent
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Shaun Knoll,Charles Jeff Morriss,Shelagh Callahan,Ajay V. Bhatt,Kottal Puthiya Nizar,Richard M. Haslam,Andrew M. Volk,Sudarshan Bala Cadambi +7 more
TL;DR: In this paper, a hierarchical serial bus assembly for serially interfacing a number of isochronous and asynchronous peripherals to the system unit of a computer system is described.
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Microprocessor having improved memory management unit and cache memory
TL;DR: In this article, the permission for a memory access in a data processing system having a virtual cache memory and a translation look-aside buffer is discussed and a determination is made based on the logical address information of the memory access operation and the permission information associated with the access operation.
Patent
Hierarchical access of test access ports in embedded core integrated circuits
TL;DR: The test access ports on an integrated circuit can be arranged in a hierarchy, with one test linking module controlling access to plural secondary test linking modules and test access access ports.
References
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Patent
Data transfer system between a computer and a host adapter using multiple arrays
TL;DR: In this article, a high speed serial link between an adapter and a data concentrator is implemented to provide inherent flow control of data, and fail safe global flow control mechanism to prevent overflow of data from the TTY devices.
Patent
Switch and its protocol for making dynamic connections
Paul Joseph Brown,Joseph Charles Elliott,Peter A. Franaszek,Karl Helmuth Hoppe,Kenneth Robert Lynch,Martin William Sachs,Leon Skarshinski +6 more
TL;DR: In this article, a dynamic switch and its protocol for establishing dynamic connections in a link by the use of frames, each frame having an identification of the source of the frame, an identity of the destination for the requested connection, and link controls to maintain, initiate or terminate a connection between the source and the destination.
Patent
System scan path architecture
TL;DR: In this article, a system scan path architecture is provided by a device select module (DSM) which may be used in conjunction with associated circuits to select secondary scan paths (PATH1-m) on each circuit for coupling with a primary scan path on a test bus.
Patent
Serial testing of removable circuit boards on a backplane bus
TL;DR: In this article, a system for controlling daisy-chain testing of removable printed circuit boards installed along a backplane bus facilitates the use of serial testing methods for circuit boards which are designed according to boundary-scan testing standards.
Patent
Partitioned scan-testing system
Jeffrey D. Bellay,Theo J. Powell +1 more
TL;DR: In this paper, a test partitionable logic circuit comprises a plurality of functional modules (26a)-(26n) interfaced with the exterior of the logic circuit with a data bus (20), address bus (16), and a control bus (12), each of the modules is addressable through an address decode/select circuit to operationally isolate the select modules and define a test boundary.
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