Journal ArticleDOI
An approach to the design of RISC core processors for VLSI embedded systems
TLDR
A fully-pipelined RISC core processor for VLSI EAs adapted to real-time MPEG video compression together with the bottom-up design methodology used are presented in this paper.About:
This article is published in Journal of Systems Architecture.The article was published on 1997-03-15. It has received 2 citations till now. The article focuses on the topics: VHDL & Very-large-scale integration.read more
Citations
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Proceedings ArticleDOI
A low-cost real-time FPGA solution for driver drowsiness detection
TL;DR: The results of the experiments show that a large number of car or trucks accidents can be avoided by detecting real-time physical and psychological states of the drivers in normal driving conditions.
Journal ArticleDOI
A High-Performance Architecture with a Macroblock-Level-Pipeline for MPEG-2 Coding
TL;DR: A high-performance parallel and pipelined architecture (MViP) has been proposed for MPEG-2 coding and a macrocell for use in an ASIC has been designed and implemented using ES2 0.7 ?
References
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Proceedings ArticleDOI
Design of an embedded video compression system-a quantitative approach
TL;DR: The paper presents the analysis environment of the CASTLE system, which supports measurement and visualization of analysis data for complex applications.
Journal ArticleDOI
Area and performance comparison of pipelined RISC processors implementing different precise interrupt methods
C.-J. Wang,F. Emnett +1 more
TL;DR: A comparative study of circuit area and performance degradation among four pipelined RISC processors using different precise interrupt methods shows that the history file method can achieve the highest performance and consume less silicon area than the reorder buffer method and the future file method.
Lazo codificador para un sistema MPEG-2 en tiempo real
TL;DR: Un sistema hardware que realiza en tiempo real las operaciones correspondientes al lazo codificador de un compresor de video basado en the norma MPEG-2 (Test Model 4.2) is described.