Vertical nanowire surrounding gate field-effect transistors (SGFETs) provide full gate control over the channel to eliminate short-channel effects and to achieve ultralow off current. This paper presents the fully depleted BSIMSOI modeling of low-power NMOS and PMOS SGFETs with 10 nm channel length and 2 nm channel radius, extraction of distributed device parasitics, and measuring the capabilities of these transistors for high-speed analog and RF applications. When biased with V ds = 0.5 V and V gs = 0.5 V at the active operating region, NMOS and PMOS SGFETs have 2 muA and 0.7 muA drain currents, 14 muA/V and 8 muA/V transconductances, 400 kOmega and 1.1 MOmega output resistances, 36 THz and 25 THz unity-current-gain cutoff frequencies, and 120 THz and 100 THz maximum frequency of oscillations, respectively. A single-stage CMOS SGFET amplifier dissipates 1.64 muW power and provides 500 GHz bandwidth with -6.5 gain and -24 dBm third-order intermodulation distortion tones for a two-tone input signal with 10 mV amplitude and 10 GHz frequency spacing. The large-signal operation of the amplifier with 1 V output swing exhibits 2.2 ps delay, 5.4 ps rise time, and 4.7 ps fall time while oscillating at 30 GHz. All these parameters indicate that vertical nanowire surrounding gate transistors are promising candidates for the next-generation very-large-scale integration (VLSI) technology.

An Exploratory Design Study of a 16 × 16 Static Random Access Memory Using Silicon Nanowire Transistors

Spice Modeling of Silicon Nanowire Field-Effect Transistors for High-Speed Analog Integrated Circuits

Vertical nanowire surrounding gate field effect transistors (SGFETs) provide full gate control over the channel to eliminate short-channel effects. This paper presents design and characterization of a differential pair amplifier using NMOS and PMOS SGFETs with a 10 nm channel length and a 2nm channel radius. The amplifier dissipates 5 µW power and provides 5THz bandwidth with a voltage gain of 16, a linear output voltage swing of 0.5 V, and a distortion better than 3% from a 1.8V power supply and a 20 aF capacitive load. The 2nd-and 3rd-order harmonic distortions of the amplifier are -40 dBm and -52 dBm, respectively, and the 3rd-order intermodulation is -24 dBm for a two-tone input signal with 10mV amplitude and 10GHz frequency spacing. All these parameters indicate that vertical nanowire surrounding gate transistors are promising candidates for the next generation high-speed analog and VLSI technologies.

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Design and characterization of the next generation nanowire amplifiers

In Chapters 1 and 2, we studied the device and digital circuit aspects of dual and single work function SNTs with the intention to minimize power dissipation. Both of these studies have determined that silicon nanowire technology is better suited for the future of VLSI in terms of circuit speed and power dissipation compared to dual-gated SOI or FiNFET technologies. These studies also included the weaknesses of SNTs such as increased layout area due to surrounding gate metal thickness, large source resistance caused by source contact extension, and limited ON current caused by fixed transistor geometry. In Chapters 1 and 2, SPICE level 6 models were used in circuit simulations. While these models had acceptable accuracy in producing speed and power dissipation figures for basic CMOS logic gates, more accurate intrinsic device modeling and parasitic RC extraction were required for simulating larger scale digital circuits, analog circuits, and Radio Frequency (RF) circuits. This need prompted us to explore more accurate SPICE models such as BSIMSOI for fully depleted Silicon-On-Insulator (SOI) devices to use in the circuit simulations. This chapter examines how the intrinsic and extrinsic BSIMSOI models were created for NMOS and PMOS SNTs.

An Exploratory Design Study of a 16 × 16 Static Random Access Memory Using Silicon Nanowire Transistors

Citations

Spice Modeling of Silicon Nanowire Field-Effect Transistors for High-Speed Analog Integrated Circuits

Design and characterization of the next generation nanowire amplifiers

SPICE Modeling for Analog and Digital Applications

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