An Integrated Design for Testability and Automatic Test Pattern Generation System: An Overview
Erwin Trischler
- pp 209-215
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TLDR
The major components of IDAS include: heuristic controllability/observability (C/O) analysis, prediction of testing costs, tools for evaluation, display and improvement of testability, and C/O guided automatic test pattern generator.Abstract:
A general overview on an Integrated Design for Testability and Automatic Test Pattern Generation System (IDAS) is given. The major components of IDAS include: heuristic controllability/observability (C/O) analysis, prediction of testing costs, tools for evaluation, display and improvement of testability, and C/O guided automatic test pattern generator. The IDAS system includes also the logic and concurrent fault simulator CADAT. A brief description of major components with a scenario how to use IDAS is given. Future research activities are discussed.read more
Citations
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Proceedings ArticleDOI
I-path analysis
TL;DR: It is shown, how the graph theory algorithms can be used to derive the information about the accessibility of circuit components, i.e., the existence of I-paths between them, and the sequences of control and clock signals which must be generated to transfer the information along the existing I- Paths.
Proceedings Article
ATWIG, an automatic test pattern generator with inherent guidance
TL;DR: Experimental results show that ATWIG is very efficient in generating test patterns for combinational and low sequential circuits and further improvements and heuristics are necessary for automatic test generation of highly sequential circuits.
Proceedings ArticleDOI
Cerberus: hierarchical DFT rule checker
R. Knopf,E. Trischler +1 more
TL;DR: The hierarchical design for testability (DFT) rule checker Cerberus has been developed to handle hierarchical circuits supporting a variety of scan structures with different types of scannable storage devices.
The integration of test and high level synthesis in a general design environment
Detlef Schmid,Raúl Camposano,Arno Kunzmann,Wolfgang Rosenstiel,Hans-Joachim Dr Rer Wunderlich +4 more
TL;DR: The integration of new tools for both test and synthesis of integrated circuits, which determines the random testability of the combinational parts of synthesized circuits and suggests optimized input signal probabilities to minimize the necessary test length are described.
Journal ArticleDOI
Bibliography of literature on testability
Balbir S. Dhillon,H.C. Viswanath +1 more
TL;DR: In this paper, a list of selected references on testability and related areas is presented, along with a brief discussion of testability in general and testability related issues in particular.
References
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Journal ArticleDOI
On the Acceleration of Test Generation Algorithms
TL;DR: The FAN (fan-out-oriented test generation algorithm) is presented, which is faster and more efficient than the PODEM algorithm reported by Goel and an automatic test generation system composed of the FAN algorithm and the concurrent fault simulation.
Journal ArticleDOI
Controllability/observability analysis of digital circuits
TL;DR: The testability of a digital circuit is directly related to the difficulty of controlling and observing the logical values of internal nodes from circuit inputs and outputs, respectively as mentioned in this paper, and the testability is also related to how well the internal nodes can be controlled and observed.
Controllability/observability analysis of digital circuits
TL;DR: The testability of a digital circuit is directly related to the difficulty of controlling and observing the logical values of internal nodes from circuit inputs and outputs, respectively as discussed by the authors, and the testability is also related to how well the internal nodes can be controlled and observed.
Proceedings ArticleDOI
SCOAP: Sandia Controllability/Observability Analysis Program
TL;DR: The testability analysis algorithms are reviewed and their implementation in the SCOAP program is described.