Journal ArticleDOI
Application-aware adaptive cache architecture for power-sensitive mobile processors
Garo Bournoutian,Alex Orailoglu +1 more
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TLDR
A novel approach to mitigating mobile processor power consumption while abating any significant degradation in execution speed is explored, which relies on efficiently leveraging both compile-time and runtime application memory behavior to intelligently target adjustments in the cache to significantly reduce overall processor power.Abstract:
Today, mobile smartphones are expected to be able to run the same complex, algorithm-heavy, memory-intensive applications that were originally designed and coded for general-purpose processors. All the while, it is also expected that these mobile processors be power-conscientious as well as of minimal area impact. These devices pose unique usage demands of ultra-portability but also demand an always-on, continuous data access paradigm. As a result, this dichotomy of continuous execution versus long battery life poses a difficult challenge. This article explores a novel approach to mitigating mobile processor power consumption while abating any significant degradation in execution speed. The concept relies on efficiently leveraging both compile-time and runtime application memory behavior to intelligently target adjustments in the cache to significantly reduce overall processor power, taking into account both the dynamic and leakage power footprint of the cache subsystem. The simulation results show a significant reduction in power consumption of approximately 13p to 29p, while only incurring a nominal increase in execution time and area.read more
Citations
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Journal ArticleDOI
Exploiting memory allocations in clusterised many-core architectures
Rafael Garibotti,Luciano Ost,Anastasiia Butko,Ricardo Reis,Abdoulaye Gamatié,Gilles Sassatelli +5 more
TL;DR: This work investigates an alternative approach that exploits on-chip data locality to a large extent, through distributed shared memory systems that permit efficient reuse of on- chip mapped data in clusterised many-core architectures.
Patent
Self-adaptive cache architecture based on run-time hardware counters and offline profiling of applications
TL;DR: In this paper, a cache memory configuration of a computing device is proposed to predict execution of an application on the computing device based on a first hardware data threshold and a first cache data.
Proceedings ArticleDOI
Way Halted Prediction Cache: An Energy Efficient Cache Architecture for Embedded Processors
TL;DR: Experimental evaluation of various SPEC benchmark programs on CACTI 5.3 and CASIM simulators reveal that the proposed architecture offers 33%, 6% and 3% savings in dynamic energy consumption and 1.95% saving in effective access time over conventional, way predicting and way halting cache architectures respectively.
Journal ArticleDOI
A Machine Learning Methodology for Cache Memory Design Based on Dynamic Instructions
TL;DR: This research presents a novel and scalable approaches called "Smart Cache Architecture (SCA)” that addresses the challenge of integrating NoSQL data stores to manage the memory demands of modern processors.
Architectural and Software Optimizations for Next- Generation Heterogeneous Low-Power Mobile Application Processors / - eScholarship
TL;DR: In this paper, the compiler-device interface is enhanced to allow more high-level application information to be relayed onto the device and underlying microarchitecture, and application-specific information is gleaned and used to optimize program execution.
References
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Proceedings ArticleDOI
MiBench: A free, commercially representative embedded benchmark suite
Matthew R. Guthaus,Jeff Ringenberg,Daniel J. Ernst,Todd Austin,Trevor Mudge,Richard B. Brown +5 more
TL;DR: A new version of SimpleScalar that has been adapted to the ARM instruction set is used to characterize the performance of the benchmarks using configurations similar to current and next generation embedded processors.
Proceedings ArticleDOI
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Proceedings ArticleDOI
Valgrind: a framework for heavyweight dynamic binary instrumentation
TL;DR: Valgrind is described, a DBI framework designed for building heavyweight DBA tools that can be used to build more interesting, heavyweight tools that are difficult or impossible to build with other DBI frameworks such as Pin and DynamoRIO.
Proceedings ArticleDOI
MediaBench: a tool for evaluating and synthesizing multimedia and communications systems
TL;DR: The MediaBench benchmark suite as discussed by the authors is a benchmark suite that has been designed to fill the gap between the compiler community and embedded applications developers, which has been constructed through a three-step process: intuition and market driven initial selection, experimental measurement, and integration with system synthesis algorithms to establish usefulness.
Journal ArticleDOI
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