Journal ArticleDOI
SimpleScalar: an infrastructure for computer system modeling
TLDR
The SimpleScalar tool set provides an infrastructure for simulation and architectural modeling that can model a variety of platforms ranging from simple unpipelined processors to detailed dynamically scheduled microarchitectures with multiple-level memory hierarchies.Abstract:
Designers can execute programs on software models to validate a proposed hardware design's performance and correctness, while programmers can use these models to develop and test software before the real hardware becomes available. Three critical requirements drive the implementation of a software model: performance, flexibility, and detail. Performance determines the amount of workload the model can exercise given the machine resources available for simulation. Flexibility indicates how well the model is structured to simplify modification, permitting design variants or even completely different designs to be modeled with ease. Detail defines the level of abstraction used to implement the model's components. The SimpleScalar tool set provides an infrastructure for simulation and architectural modeling. It can model a variety of platforms ranging from simple unpipelined processors to detailed dynamically scheduled microarchitectures with multiple-level memory hierarchies. SimpleScalar simulators reproduce computing device operations by executing all program instructions using an interpreter. The tool set's instruction interpreters also support several popular instruction sets, including Alpha, PPC, x86, and ARM.read more
Citations
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Journal ArticleDOI
The worst-case execution-time problem—overview of methods and survey of tools
Reinhard Wilhelm,Jakob Engblom,Andreas Ermedahl,Niklas Holsti,Stephan Thesing,David Whalley,Guillem Bernat,Christian Ferdinand,Reinhold Heckmann,Tulika Mitra,Frank Mueller,Isabelle Puaut,Peter Puschner,Jan Staschulat,Per Stenström +14 more
TL;DR: Different approaches to the determination of upper bounds on execution times are described and several commercially available tools1 and research prototypes are surveyed.
Journal ArticleDOI
Multifacet's general execution-driven multiprocessor simulator (GEMS) toolset
Milo M. K. Martin,Daniel J. Sorin,Bradford M. Beckmann,Michael R. Marty,Min Xu,Alaa R. Alameldeen,Kevin E. Moore,Mark D. Hill,Darien Wood +8 more
TL;DR: The Wisconsin Multifacet Project has created a simulation toolset to characterize and evaluate the performance of multiprocessor hardware systems commonly used as database and web servers as mentioned in this paper, which includes a set of timing simulator modules for modeling the timing of the memory system and microprocessors.
Multifacets General Execution-Driven Multiprocessor Simulator (GEMS) Toolset
TL;DR: The Wisconsin Multifacet Project has created a simulation toolset to characterize and evaluate the performance of multiprocessor hardware systems commonly used as database and web servers and has released a set of timing simulator modules for modeling the timing of the memory system and microprocessors.
Proceedings ArticleDOI
Razor: a low-power pipeline based on circuit-level timing speculation
Daniel J. Ernst,Nam Sung Kim,Shidhartha Das,Sanjay Pant,Rajeev R. Rao,Toan Pham,Conrad H. Ziesler,David Blaauw,Todd Austin,Krisztian Flautner,Trevor Mudge +10 more
TL;DR: A solution by which the circuit can be operated even below the ‘critical’ voltage, so that no margins are required and thus more energy can be saved.
Proceedings ArticleDOI
GARNET: A detailed on-chip network model inside a full-system simulator
TL;DR: In this article, a detailed cycle-accurate interconnection network model (GARNET) is proposed to simulate a CMP architecture with virtual channel (VC) flow control.
References
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Proceedings ArticleDOI
Wattch: a framework for architectural-level power analysis and optimizations
TL;DR: Wattch is presented, a framework for analyzing and optimizing microprocessor power dissipation at the architecture-level and opens up the field of power-efficient computing to a wider range of researchers by providing a power evaluation methodology within the portable and familiar SimpleScalar framework.
Proceedings ArticleDOI
Energy-driven integrated hardware-software optimizations using SimplePower
TL;DR: The design and use of the SimplePower framework is presented that includes a transition-sensitive, cycle-accurate datapath energy model that interfaces with analytical and transition sensitive energy models for the memory and bus subsystems, respectively.
Proceedings ArticleDOI
Measuring experimental error in microprocessor simulation
TL;DR: The methodology that was used to validate a microprocessor simulator against a Compaq DS-10L workstation, which contains an Alpha 21264 processor, and how low-level optimizations reduce average error from 40% to less than 20% on macrobenchmarks drawn from the SPEC2000 suite is described.
Proceedings Article
Validating the Intel® Pentium® 4 Microprocessor
TL;DR: The purpose of this paper is to provide data on the bugs that were found prior to initial silicon on the Pentium®4 processor, and to describe how the team went about the task of finding them.
Journal ArticleDOI
Fast out-of-order processor simulation using memoization
Eric Schnarr,James R. Larus +1 more
TL;DR: This new out-of-order processor simulatol; FastSim, uses a variation on memoization to cache microarchitecture states and the resulting simulator actions, and then "fast forwards" the simulation the next time a cached state is reached.