Proceedings ArticleDOI
Automated synthesis of large phase shifters for built-in self-test
Janusz Rajski,Nagesh Tamarapalli,Jerzy Tyszer +2 more
- pp 1047-1056
TLDR
The paper introduces a new algorithm for the automated synthesis of phase shifters-circuits used to remove effects of structural dependencies featured by two-dimensional test generators in a time-efficient manner.Abstract:
The paper introduces a new algorithm for the automated synthesis of phase shifters-circuits used to remove effects of structural dependencies featured by two-dimensional test generators. The algorithms presented in the paper synthesize in a time-efficient manner very large and fast phase shifters for built in self-test environment, with guaranteed minimal phase shifts between scan chains, and very low delay and area of virtually one 2-way XOR gate per channel.read more
Citations
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Proceedings ArticleDOI
Logic BIST for large industrial designs: real issues and case studies
TL;DR: The experimental results demonstrate that with automation of the proposed solutions, logic BIST can achieve test quality approaching that of ATPG with minimal area overhead and few changes to the design flow.
Proceedings ArticleDOI
Adapting scan architectures for low power operation
TL;DR: A method of adapting conventional scan architectures such that they operate in a low power mode during test so that they maintain the test times of the pre-adapted scan architectures.
Proceedings ArticleDOI
Reducing test data volume using LFSR reseeding with seed compression
C.V. Krishna,Nur A. Touba +1 more
TL;DR: A new lossless test vector compression scheme is presented which combines linear feedback shift register (LFSR) reseeding and statistical coding in a powerful way to improve the encoding efficiency.
Patent
Test pattern compression for an integrated circuit test environment
TL;DR: In this paper, a method for compressing test patterns to be applied to scan chains in a circuit under test is presented, which includes generating symbolic expressions associated with scan cells within the scan chains.
Patent
Method and apparatus for selectively compacting test responses
TL;DR: In this article, a linear compactor with a selection circuitry for selectively passing test responses to the compactor is proposed, where a gating logic is controlled by a control register, a decoder, and flag registers.
References
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Book
The Art of Computer Programming
TL;DR: The arrangement of this invention provides a strong vibration free hold-down mechanism while avoiding a large pressure drop to the flow of coolant fluid.
Book
Built In Test for VLSI: Pseudorandom Techniques
TL;DR: Digital Testing and the Need for Testable design Principles of Testable Design Pseudorandom Sequence Generators Test Response Compression Techniques and Limitations and Other Concerns of Random Pattern Testing Test System Requirements for Built-In Test Appendix References Index.
Journal ArticleDOI
Built-in test for circuits with scan based on reseeding of multiple-polynomial linear feedback shift registers
TL;DR: A new scheme for built-in test that uses multiple-polynomial linear feedback shift registers (MP-LFSR's) and an implicit polynomial identification reduces the number of extra bits per seed to one bit is presented.
Proceedings ArticleDOI
Decompression of test data using variable-length seed LFSRs
TL;DR: A new and efficient scheme to decompress a set of deterministic test vectors for circuits with scan based on the reseeding of a Multiple Polynomial Linear Feedback Shift Register but uses variable-length seeds to improve the encoding efficiency of test vectors with a wide variation in their number of specified bits.