Open AccessBook
Built In Test for VLSI: Pseudorandom Techniques
TLDR
Digital Testing and the Need for Testable design Principles of Testable Design Pseudorandom Sequence Generators Test Response Compression Techniques and Limitations and Other Concerns of Random Pattern Testing Test System Requirements for Built-In Test Appendix References Index.Abstract:
Digital Testing and the Need for Testable Design Principles of Testable Design Pseudorandom Sequence Generators Test Response Compression Techniques Shift-Register Polynomial Division Special-Purpose Shift-Register Circuits Random Pattern Built-In Test Built-In Test Structures Limitations and Other Concerns of Random Pattern Testing Test System Requirements for Built-In Test Appendix References Index.read more
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Book
VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon)
TL;DR: This book is a comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time-to-market and time- to-volume.
Proceedings ArticleDOI
Estimation of average switching activity in combinational and sequential circuits
TL;DR: The authors address the problem of estimating the average power dissipated in VLSI combinational and sequential circuits, under random input sequences, by presenting methods to probabilistically estimate switching activity in sequential circuits.
Statistical Signal Processing
TL;DR: An understanding of the convergence and synchronization of statistical signal processing algorithms in continuous time is developed, and an understanding of linear and nonlinear circuits for analog memory is explored, and the “soft-multiplexer” is proposed.
Journal ArticleDOI
Built-in test for circuits with scan based on reseeding of multiple-polynomial linear feedback shift registers
TL;DR: A new scheme for built-in test that uses multiple-polynomial linear feedback shift registers (MP-LFSR's) and an implicit polynomial identification reduces the number of extra bits per seed to one bit is presented.
Book
VLSI Test Principles and Architectures: Design for Testability
TL;DR: A comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time to market and time-to-volume as mentioned in this paper.