Proceedings ArticleDOI
Logic BIST for large industrial designs: real issues and case studies
Graham G. Hetherington,T. Fryars,Nagesh Tamarapalli,M. Kassab,A. Hassan,Janusz Rajski +5 more
- pp 358-367
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TLDR
The experimental results demonstrate that with automation of the proposed solutions, logic BIST can achieve test quality approaching that of ATPG with minimal area overhead and few changes to the design flow.Abstract:
This paper discusses practical issues involved in applying logic built-in self-test (BIST) to four large industrial designs. These multi-clock designs, ranging in size from 200 K to 800 K gates, pose significant challenges to logic BIST methodology, flow, and tools. The paper presents the process of generating a BIST-compliant core along with the logic BIST controller for at-speed testing. Comparative data on fault grades and area overhead between automatic test pattern generation (ATPG) and logic BIST are reported. The experimental results demonstrate that with automation of the proposed solutions, logic BIST can achieve test quality approaching that of ATPG with minimal area overhead and few changes to the design flow.read more
Citations
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Journal ArticleDOI
Embedded deterministic test
TL;DR: This paper presents a novel test-data volume-compression methodology called the embedded deterministic test (EDT), which reduces manufacturing test cost by providing one to two orders of magnitude reduction in scan test data volume and scan test time.
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VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon)
TL;DR: This book is a comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time-to-market and time- to-volume.
Proceedings ArticleDOI
Embedded deterministic test for low cost manufacturing test
Janusz Rajski,Jerzy Tyszer,M. Kassab,Nilanjan Mukherjee,Rob Thompson,Kun-Han Tsai,A. Hertwig,Nagesh Tamarapalli,Grzegorz Mrugalski,Geir Eide,Jun Qian +10 more
TL;DR: Embedded deterministic test technology is introduced, which reduces manufacturing test cost by providing one to two orders of magnitude reduction in scan test data volume and scan test time.
Journal ArticleDOI
System-on-a-chip test-data compression and decompression architectures based on Golomb codes
TL;DR: A new test-data compression method and decompression architecture based on variable-to-variable-length Golomb codes that is especially suitable for encoding precomputed test sets for embedded cores in a system-on-a-chip (SoC).
Proceedings ArticleDOI
OPMISR: the foundation for compressed ATPG vectors
Carl F. Barnhart,V. Brunkhorst,Frank O. Distler,O. Farnsworth,Brion L. Keller,Bernd Karl Ferdinand Koenemann +5 more
TL;DR: Techniques are presented in this paper that allow for substantial compression of Automatic Test Pattern Generation (ATPG) produced test vectors, allowing for a more than 10-fold reduction in tester scan buffer data volume on ATPG compacted tests.
References
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Book
Built In Test for VLSI: Pseudorandom Techniques
TL;DR: Digital Testing and the Need for Testable design Principles of Testable Design Pseudorandom Sequence Generators Test Response Compression Techniques and Limitations and Other Concerns of Random Pattern Testing Test System Requirements for Built-In Test Appendix References Index.
Journal ArticleDOI
Built-In Self-Test Techniques
TL;DR: The various linear-feedback shift register designs for pseudorandom or pseudoexhaustive input test pattern generation and for output response signature analysis are presented.
Proceedings ArticleDOI
Constructive multi-phase test point insertion for scan-based BIST
N. Tamarapalli,Janusz Rajski +1 more
TL;DR: Experimental results demonstrate that complete or near-complete stuck-at fault coverage can be achieved by the proposed technique with the insertion of a few test points and a minimum number of phases.
Proceedings ArticleDOI
Automated synthesis of large phase shifters for built-in self-test
TL;DR: The paper introduces a new algorithm for the automated synthesis of phase shifters-circuits used to remove effects of structural dependencies featured by two-dimensional test generators in a time-efficient manner.
Proceedings ArticleDOI
PSBIST: A partial-scan based built-in self-test scheme
TL;DR: Partial-scan based built-in self-test (PSBIST) is a versatile design for testability (DFT) scheme, which employs pseudo-random BIST at all levels of test to achieve fault coverages greater than 98% on average, and supports deterministic partial scan at the IC level to achieve nearly 100% fault coverage.