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Proceedings ArticleDOI

Automatic Pattern Generation for Diagnosis of Wiring Interconnect Faults

M. Melton, +1 more
- pp 389-398
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TLDR
A unified approach to automatic pattern generation for diagnosis of board-level wiring defects between modules both with and without boundary scan is introduced and the number of patterns for complete diagnosis compares favorably with patterns required for first detection of single stuck-at faults only.
Abstract
This paper introduces a unified approach to automatic pattern generation for diagnosis of board-level wiring defects between modules both with and without boundary scan. The fault model for wiring defects includes bridging faults, stuck-at faults and open faults. We show that complete diagnosis of 1/0 faults can be achieved by considering single faults only rather than fault pairs and we have modified a traditional sptem that supports single stuck fault test generation to also perform pattern generation for complete diagnosis. Rather than building a fault dictionary from detection patterns, we introduce distinguishing functions, a fault diagnosis tree and heuristics to resolve signatures of faults so that they become unique or are proven equivalent. Experimental results with large benchmark circuits show that complete diagnosis for stuck-at as well as bridging I/O faults is possible. The number of patterns for complete diagnosis compares favorably with patterns required for first detection of single stuck-at faults only.

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Citations
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Proceedings ArticleDOI

Diagnosis of interconnects and FPICs using a structured walking-1 approach

TL;DR: A generalized new approach for testing interconnects (for boundary scan architectures) as well as field programmable interconnect chips (FPICs) and the applicability of the proposed approach to FPICs is discussed and evaluated by simulation.
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Fault behavior dictionary for simulation of device-level transients

TL;DR: In this article, the authors present a methodology for the simulation of massive number of device-level transient faults and evaluate the fault injection locations and the gate around those locations with SPICE.
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A pragmatic test and diagnosis methodology for partially testable MCMs

TL;DR: This paper proposes a methodology for simultaneous test and diagnosis of boundary scan and non boundary scan parts and presents a way to get along with partial testability.
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Introduction of permissible bridges with application to logic optimization after technology mapping

B. Rohfleisch, +1 more
TL;DR: This paper exploits the conditional equivalence of wire pairs and shows that even after technology mapping, it can significantly reduce the active area as well as the wiring of many designs.
Journal ArticleDOI

A sweeping line approach to interconnect testing

TL;DR: It is proved that the problem of generating the minimum number of test vectors by compaction is NP-complete, but simulation results show that the proposed heuristic criteria are very efficient for a practical application.
References
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Book

Digital Systems Testing and Testable Design

TL;DR: The new edition of Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems offers comprehensive and state-ofthe-art treatment of both testing and testable design.
Book

The Test Access Port and Boundary Scan Architecture

TL;DR: In this article, a wheel decorating ornament comprising an annular, planar sheet of material decorated on opposite sides, axially disposed between the groups of spokes and radially disposed at the rim and the hub, is presented.
Proceedings ArticleDOI

A new framework for analyzing test generation and diagnosis algorithms for wiring interconnects

TL;DR: A novel framework for analyzing test generation and diagnosis algorithms for wiring interconnect are presented, and a property of test vector sets, called diagonal independence, which guarantees the diagnostic resolution of the vector test set is identified.
Proceedings ArticleDOI

Testing and diagnosis of interconnects using boundary scan architecture

TL;DR: A built-in self-test of interconnects based on boundary scan architecture is described in this paper, where detection and diagnosis schemes are proposed which provide minimal-size test vector sets.