Proceedings ArticleDOI
Behavioral synthesis for easy testability in data path scheduling
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TLDR
In this paper, a data path scheduling algorithm to improve testability without assuming any particular test strategy is presented, and a scheduling heuristic for easy testability, based on previous work on data path allocation for testability is introduced.Abstract:
A data path scheduling algorithm to improve testability without assuming any particular test strategy is presented. A scheduling heuristic for easy testability, based on previous work on data path allocation for testability, is introduced. A mobility path scheduling algorithm to implement this heuristic while also minimizing area is developed. Experimental results on benchmark and example circuits show high fault coverage, short test generation time, and little or no area overhead. >read more
Citations
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Proceedings ArticleDOI
Behavioral Synthesis of Highly Testable Data Paths under the Non-Scan and Partial Scan Environments
TL;DR: A new behavioral synthesis algorithm for testability which reduces sequential loop size while minimizing area and considers two levels of testability synthesis: synthesis for non-scan, which assumes no test strategy beforehand; and synthesis for partial scan, which uses the available scan information during resource allocation.
Proceedings ArticleDOI
High-level synthesis for testability: a survey and perspective
Kenneth D. Wagner,Sujit Dey +1 more
TL;DR: This work reviews behavioral and RTL test synthesis and synthesis for testability approaches that generate easily testable implementations and an overview of high-level synthesis techniques to assist high- level ATPG.
Proceedings ArticleDOI
Arithmetic built-in self test for high-level synthesis
TL;DR: An entirely new Built-in Self Test scheme for high-level synthesis of data path architectures that makes use of the arithmetic blocks in the data path to generate test vectors and compact test responses is proposed.
Proceedings ArticleDOI
Enhancing high-level control-flow for improved testability
TL;DR: Experimental results on several high-level synthesis benchmarks show that when this approach is used prior to logic synthesis, a shorter ATPG time, a smaller test set, and better fault coverage and ATPG efficiency are often achieved.
Proceedings ArticleDOI
Exploiting hardware sharing in high-level synthesis for partial scan optimization
TL;DR: The paper introduces the problem of breaking CDFG loops with a minimal number of scan registers, and demonstrates the effectiveness of the technique to synthesize easily testable data paths, with significantly less partial scan cost than a gate-level partial scan approach.
References
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Journal ArticleDOI
The high-level synthesis of digital systems
TL;DR: It is shown how the high-level synthesis task can be decomposed into a number of distinct but not independent subtasks.
Proceedings ArticleDOI
Sequential circuit design using synthesis and optimization
E.M. Sentovich,K.J. Singh,Cho W. Moon,Hamid Savoj,Robert K. Brayton,Alberto Sangiovanni-Vincentelli +5 more
TL;DR: SIS serves as both a framework within which various algorithms can be tested and compared and as a tool for automatic synthesis and optimization of sequential circuits.
Proceedings ArticleDOI
MAHA: A Program for Datapath Synthesis
TL;DR: MAHA is a program which implements an algorithm for register level synthesis of data paths from a data flow specification based on a linear hardware assignment to critical path nodes, followed by a cost-based assignment using the concept of the freedom of a node to be scheduled.
Proceedings ArticleDOI
HAL: A Multi-Paradigm Approach to Automatic Data Path Synthesis
TL;DR: A novel approach to automatic data path synthesis is presented, which features innovations in the synthesis process as well as in the system implementation that supports extended design space search by taking an explicit performance specification into account.
BookDOI
High-Level VLSI Synthesis
Raul Camposano,Wayne Wolf +1 more
TL;DR: This chapter discusses architectural Synthesis for Medium and High Throughput Signal Processing with the new CATHEDRAL environment, and high-Level Synthesis in the THEDA System.