Journal ArticleDOI
The high-level synthesis of digital systems
Michael C. McFarland,Alice C. Parker,Raul Camposano +2 more
- Vol. 78, Iss: 2, pp 301-318
TLDR
It is shown how the high-level synthesis task can be decomposed into a number of distinct but not independent subtasks.Abstract:
High-level synthesis systems start with an abstract behavioral specification of a digital system and find a register-transfer level structure that realizes the given behavior. The various tasks involved in developing a register-transfer level structure from an algorithmic level specification are described. In particular, it is shown how the high-level synthesis task can be decomposed into a number of distinct but not independent subtasks. The techniques that have been developed for solving those subtasks are presented. Areas related to high-level synthesis that are still open problems are examined. >read more
Citations
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Journal ArticleDOI
Hardware-software co-design of embedded systems
TL;DR: A historical approach is emphasized to show the relationships between well-understood design problems and the as-yet unsolved problems in co-design.
Journal ArticleDOI
Static rate-optimal scheduling of iterative data-flow programs via optimum unfolding
Abstract: Rate-optimal compile-time multiprocessor scheduling of iterative dataflow programs suitable for real-time signal processing applications is discussed. It is shown that recursions or loops in the programs lead to an inherent lower bound on the achievable iteration period, referred to as the iteration bound. A multiprocessor schedule is rate-optimal if the iteration period equals the iteration bound. Systematic unfolding of iterative dataflow programs is proposed, and properties of unfolded dataflow programs are studied. Unfolding increases the number of tasks in a program, unravels the hidden concurrently in iterative dataflow programs, and can reduce the iteration period. A special class of iterative dataflow programs, referred to as perfect-rate programs, is introduced. Each loop in these programs has a single register. Perfect-rate programs can always be scheduled rate optimally (requiring no retiming or unfolding transformation). It is also shown that unfolding any program by an optimum unfolding factor transforms any arbitrary program to an equivalent perfect-rate program, which can then be scheduled rate optimally. This optimum unfolding factor for any arbitrary program is the least common multiple of the number of registers (or delays) in all loops and is independent of the node execution times. An upper bound on the number of processors for rate-optimal scheduling is given. >
Patent
Method and system for creating and validating low level description of electronic design
TL;DR: In this article, a methodology for generating structural descriptions of complex digital devices from high-level descriptions and specifications is described, which uses a systematic technique to map and enforce consistency of the semantics imbedded in the original, highlevel descriptions.
Journal ArticleDOI
Path-based scheduling for synthesis
TL;DR: A novel path-based scheduling algorithm that yields solutions with the minimum number of control steps, taking into account arbitrary constraints that limit the amount of operations in each control step, is presented.
Book
The Zynq Book: Embedded Processing with the Arm Cortex-A9 on the Xilinx Zynq-7000 All Programmable Soc
TL;DR: This book is about the Zynq-7000 All Programmable System on Chip, the family of devices from Xilinx that combines an application-grade ARM Cortex-A9 processor with traditional FPGA logic fabric.
References
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Book
Computers and Intractability: A Guide to the Theory of NP-Completeness
TL;DR: The second edition of a quarterly column as discussed by the authors provides a continuing update to the list of problems (NP-complete and harder) presented by M. R. Garey and myself in our book "Computers and Intractability: A Guide to the Theory of NP-Completeness,” W. H. Freeman & Co., San Francisco, 1979.
Journal ArticleDOI
Automated Synthesis of Data Paths in Digital Systems
TL;DR: This paper presents a unifying procedure, called Facet, for the automated synthesis of data paths at the register-transfer level that minimizes the number of storage elements, data operators, and interconnection units.
Journal ArticleDOI
Sehwa: a software package for synthesis of pipelines from behavioral specifications
N. Park,Alice C. Parker +1 more
TL;DR: Sehwa can find the minimum-cost design, the highest performance design, and other designs between these two in the design space and executes within minutes, for problems of practical size, on a VAX 11/750.
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Sehwa: a software package for synthesis of pipelines from behavioral specifications
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