Open Access
BIST-Based Diaignostics of FPGA Logic Bllocks
TLDR
The first approach able to diagnose faulty programmable logic blocks (PLBs) in Field Programmable Gate Arrays (FPGAs) with maximal cliagnos- tic resolution is presented, based on a new Built-In Self- Test (BIST) architecture for FPGAs and can accurately locate any single and most multiple faulty l?LBs.Abstract:
Accurate diagnosis is an essential requirement in many testing environments, since it is the basis for any repair or replacement strategy used for chip or system fault-toler- ance. In this paper we present the: first approach able to diagnose faulty programmable logic blocks (PLBs) in Field Programmable Gate Arrays (FPGAs) with maximal cliagnos- tic resolution. Our approach is basecl on a new Built-In Self- Test (BIST) architecture for FPGAs and can accurately locate any single and most multiple faulty l?LBs. An adaptive diag- nostic strategy provides identification of faulty PLB!j with a 7% increase in testing time over the complete detect.ion test, and can also be used for manufacturing yield einhanlcement. We present results showing identification of faulty I'LBs in defective ORCA chips.' 1.Introducti.on An FPGA consists of an array of programmable logic blocks (PLBs) interconnected by a programm,able routing network, and programmable U0 cells. The set of all program- ming bits establishes a cnnjiguration which determines the function of the device. In this paper, we considler in-circuit reprogrammable FPGAs, such as SRAM-based FPGAs, which may be reconfigured an arbitrarily large: number of times. FPGA manufacturing tests are complicated by the need to cover all possible modes of operation of the PLBs and also to detect all the faults affecting the programmable inter- connect network. Currently, thesje tests are generated manually by configuring several application circuits and exercising them with test patterns developed specifically for each application circuit. The FPGA manufacturing tiests are not reusable for board and system-level testing, which require separate development efforts that rely on system diagnostic routines to test the FPGAs in their system mode of operation. The development of these diagnostic routines can be time- consuming and costly, and locating a faulty FPGA may be difficult. Previous work in FPGA te~ting(~~(~~('* ~(''~read more
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Dissertation
Diagnosticabilité modulaire appliquée au Diagnostic en ligne des Systèmes Embarqués Logiques
TL;DR: In this paper, a nouvelle approche de modelisation des systemes embarques temporises for le diagnostic de leurs fautes is proposed, based on a decomposition structure of the systeme and an extension of the diagnosticabilite modulaire.
References
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Verification Testing—A Pseudoexhaustive Test Technique
TL;DR: A new approach to test pattern generation which is particularly suitable for self-test is described, which requires much less computation time and fault coverage is much higher—all irredundant multiple as well as single stuck faults are detected.
Proceedings ArticleDOI
Built-in self-test of logic blocks in FPGAs (Finally, a free lunch: BIST without overhead!)
TL;DR: A new approach for Field Programmable Gate Array (FPGA) testing is presented that exploits the reprogrammability of FPGAs to create Built-In Self-Test (BIST) logic only during off-line test, achieving BIST without any area overhead or performance penalties to the system function implemented by the FPGA.
Proceedings ArticleDOI
Defect tolerance on the Teramac custom computer
TL;DR: This work has developed methods to precisely locate defects in Teramac, a large custom computer which works correctly despite the fact that three quarters of its FPGAs contain defects.
Journal ArticleDOI
Design of Easily Testable Bit-Sliced Systems
TL;DR: I-testability ensures that identical test responses can be obtained from every cell in an ILA, and thus simplifies response verification, and the application of C- and I-testing to the design of bit-sliced (micro-) computers is investigated.
Proceedings ArticleDOI
Diagnosing Programmable Interconnect Systems for FPGAs
TL;DR: A hierarchical approach to diagnosis of field programmable interconnect systems in which nets are connected through programmable switches arranged in grids is proposed and the conditions by which such process yields full diagnosis are fully proved.