Journal ArticleDOI
Verification Testing—A Pseudoexhaustive Test Technique
TLDR
A new approach to test pattern generation which is particularly suitable for self-test is described, which requires much less computation time and fault coverage is much higher—all irredundant multiple as well as single stuck faults are detected.Abstract:
A new approach to test pattern generation which is particularly suitable for self-test is described. Required computation time is much less than for present day automatic test pattern generation (ATPG) programs. Fault simulation or fault modeling is not required. More patterns may be obtained than from standard ATPG programs. However, fault coverage is much higher—all irredundant multiple as well as single stuck faults are detected. The test patterns are easily generated algorithmically either by program or hardware.read more
Citations
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Book
VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon)
TL;DR: This book is a comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time-to-market and time- to-volume.
Journal ArticleDOI
Built-In Self-Test Techniques
TL;DR: The various linear-feedback shift register designs for pseudorandom or pseudoexhaustive input test pattern generation and for output response signature analysis are presented.
Book
VLSI Test Principles and Architectures: Design for Testability
TL;DR: A comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time to market and time-to-volume as mentioned in this paper.
Book
Electronic Design Automation: Synthesis, Verification, and Test
TL;DR: EDA/VLSI practitioners and researchers in need of fluency in an "adjacent" field will find this an invaluable reference to the basic EDA concepts, principles, data structures, algorithms, and architectures for the design, verification, and test of VLSI circuits.
Proceedings ArticleDOI
Using a single input to support multiple scan chains
TL;DR: By appropriately connecting the inputs of all circuits under test during ATPG process such that the generated test patterns can be broadcast to all scan chains when actual testing is executed, it is shown that 177 and 280 test patterns are enough to detect all detectable faults in all 10 ISCas'85 combinational circuits and 10 largest ISCAS'89 sequential circuits.
References
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Proceedings ArticleDOI
A logic design structure for LSI testability
TL;DR: A logic design method that will greatly simplify problems in testing, diagnostics, and field service for LSI is described, based on two concepts that are nearly independent but combine efficiently and effectively.
Journal ArticleDOI
Design for testability—A survey
T.W. Williams,Kenneth P. Parker +1 more
TL;DR: A short review of the basics of testability is given in this paper along with some reasons why one should test and different techniques of design for testability are discussed in detail, including techniques which can be applied to today's technologies and techniques which have been recently introduced and will soon appear in new designs.
Journal ArticleDOI
Random Pattern Testability
TL;DR: A new analytical method of computing the fault coverage that is fast compared with simulation is described that is possible to identify the ``random-pattern-resistant'' faults, modify the logic to make them easy to detect, and thus, increase the fault Coverage of the random test.
Journal ArticleDOI
Design for Autonomous Test
McCluskey,Bozorgui-Nesbat +1 more
TL;DR: A technique for modifying networks so that they are capable of self test is presented, partitioning the network into subnets with sufficiently few inputs that exhaustive testing of the subnetworks is possible.
Journal ArticleDOI
Random-pattern coverage enhancement and diagnosis for LSSD logic self-test
E. B. Eichelberger,E. Lindbloom +1 more
TL;DR: Embedded linear feedback shift registers can be used for logic component self-test and a procedure that supports net-level diagnosis for structured logic in the presence of random test-pattern generation and signature analysis is given.