Proceedings ArticleDOI
CBSC-based pipelined analog-to-digital converters: Power dissipation bound analysis
Majid Zamani,Clemens Eder,Andreas Demosthenous +2 more
- pp 436-439
TLDR
The objective of this paper is to derive the theoretical minimum power dissipation bound for CBSC-based pipelined ADCs with digital error correction of 1.5 bit/stage through behavioral simulation in MATLAB.Abstract:
The comparator-based switched-capacitor (CBSC) technique has been used in low power analog-to-digital converters (ADCs). The objective of this paper is to derive the theoretical minimum power dissipation bound for CBSC-based pipelined ADCs with digital error correction of 1.5 bit/stage. To achieve this, the constituent building blocks whose performance is limited by noise, are examined. The optimum values of the design parameters influencing the power dissipation bound are also investigated including the optimal output ramp rates needed to achieve a given linearity constraint, comparator bias current and delay time. The derived equations are verified through behavioral simulation in MATLAB.read more
Citations
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Proceedings ArticleDOI
Analog-to-digital converters power dissipation limits of CBSC-based pipelined
TL;DR: The constituent building blocks whose performance is limited by noise, are examined to derive the theoretical power bound for CBSC-based pipelined ADCs with digital error correction (1.5 bit/stage).
References
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CMOS Circuit Design, Layout, and Simulation
TL;DR: Regardless of one's integrated circuit (IC) design skill level, this book allows readers to experience both the theory behind, and the hands-on implementation of, complementary metal oxide semiconductor (CMOS) IC design via detailed derivations, discussions, and hundreds of design, layout, and simulation examples.
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TL;DR: This chapter discusses the design and simulation of delta-sigma modulator systems, and some of the considerations for implementation considerations for [Delta][Sigma] ADCs.
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Analog circuits in ultra-deep-submicron CMOS
TL;DR: In this paper, the gate-leakage mismatch exceeds conventional matching tolerances, and the drop in supply voltages can solve this problem by exploiting combinations of thin and thick-oxide transistors.
Proceedings ArticleDOI
Comparator-based switched-capacitor circuits for scaled CMOS technologies
TL;DR: A comparator-based switched-capacitor circuit (CBSC) technique is presented for the design of analog and mixed-signal circuits in scaled CMOS technologies.